Shielded multi-conductor interconnect bus for MEMS

Details Shielded multi-conductor interconnect bus for MEMS Shielded multi-conductor interconnect bus for MEMS

2002-03-15

2004-05-04

Zarneke, David A. (Department: 2827)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S803000, C361S818000, C174S034000, C257S659000

Reexamination Certificate

active

06731513

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to microelectromechanical systems (MEMS), and more particularly to the design and fabrication of interconnect architectures for MEMS.
BACKGROUND OF THE INVENTION
MEMS can include numerous electromechanical devices fabricated on a single substrate, many of which are to be separately actuated in order to achieve a desired operation. For example, a MEMS optical switch may include numerous mirrors that are each positionable in a desired orientation for reflecting optical signals between originating and target locations upon actuation of one or more microactuators associated with each mirror. In order for each mirror to be separately positioned, separate control signals need to be supplied to the microactuators associated with each mirror. One manner of accomplishing this is to connect each microactuator to a control signal source with a separate electrical conductor (i.e., an interconnect line) fabricated on the surface of the substrate that extends between its associated microactuator and a bond pad at the periphery of the substrate where it can be easily connected to an off-chip control signal source. In this regard, the separate interconnect lines together comprise an interconnect bus and are typically arranged to run parallel with each other for substantial portions of their length.
As may be appreciated, the amount of footprint required on the surface of the substrate for an interconnect bus is an important factor in designing MEMS since increasing the footprint of the interconnect bus decreases the amount of footprint available for desired devices (e.g., mirrors and actuators). Another consideration is possible cross-talk between the separate interconnect lines. Cross-talk is a problem because a control signal intended for one actuator can be coupled from its interconnect line into adjacent interconnect lines causing undesired actuation of other actuators. A further consideration is the possibility of shorting between adjacent interconnect lines. Where the interconnect bus lines are exposed on the surface of the substrate, particles and the like can settle across adjacent interconnect lines thereby causing short circuits effecting operation of the MEMS.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a shielded multi-conductor interconnect bus for MEMS and a method for fabricating such an interconnect bus. The shielded multi-conductor interconnect bus of the present invention substantially reduces the possibility of cross-talk between adjacent interconnect lines, alleviates the possibility of short circuits due to particles and the like settling across adjacent interconnect lines, and optimizes the amount of footprint required for such an interconnect bus.
According to one aspect of the present invention, a shielded multi-conductor interconnect bus includes a substrate. The substrate may, for example, be comprised of silicon. A first dielectric layer overlies and is supported by at least a portion of the substrate. In this regard, the first dielectric layer may, for example, be the lowest layer of material on the substrate (i.e., it may be formed directly on the upper surface of the substrate without any intervening layers). In one embodiment, the substrate is comprised of silicon and the first dielectric layer comprises a dielectric stack deposited directly on the upper surface of the substrate that includes a lower thermal oxide layer and an upper silicon nitride layer. A plurality of substantially parallel electrically conductive lines are formed on the first dielectric layer. In this regard, the electrically conductive lines may be formed from a first layer of doped polysilicon.
The interconnect bus also includes a plurality of substantially parallel electrically conductive walls formed on the first dielectric layer. Although desirable, it should be understood that electrically conductive walls described herein do not have to be continuous along their lengthwise extent and may, in fact, have one or more breaks formed therein as desired. Each electrically conductive wall includes an upper section that extends vertically above the level of the electrically conductive lines. There may also be a plurality of substantially parallel channels formed in the first dielectric layer with lower sections of the electrically conductive walls being formed in the channels. In this regard, the lower sections of the electrically conductive walls may be formed from the first layer of doped polysilicon and the upper sections of the electrically conductive walls may be formed from a second layer of doped polysilicon. The second layer of doped polysilicon may be comprised of a thinner lower layer of doped polysilicon and a thicker upper layer of doped polysilicon. Where the first dielectric layer is the lowest layer of material on the substrate, each channel preferably extends vertically downward through the entire thickness of the first dielectric layer to expose the upper surface of the substrate along at least a portion of each channel, and, more preferably, along the entire length of each channel.
The electrically conductive lines and electrically conductive walls are arranged in pattern such that an electrically conductive wall is located between adjacent sets of the electrically conductive lines. In this regard, each set of electrically conductive lines includes at least one of the electrically conductive lines, and may include two or more electrically conductive lines.
In addition to separating adjacent sets of electrically conductive lines, the electrically conductive walls also contact the underside of an electrically conductive shield positioned in a spaced relation above the electrically conductive lines. The electrically conductive shield may be formed from the second layer of doped polysilicon. In one embodiment, there is a second dielectric layer beneath the electrically conductive shield overlying the electrically conductive lines and the first dielectric layer. The second dielectric layer may be comprised of a sacrificial material (e.g., silicon dioxide or silicate glass). The second dielectric layer includes a plurality of channels formed therein permitting the upper sections of the electrically conductive walls to extend vertically upward therethrough to contact the underside of the electrically conductive shield. Thus, each electrically conductive line is surrounded by dielectric material, and each set of electrically conductive lines is electrically isolated from the other sets of electrically conductive lines within, what is in effect, an equipotential tube comprising the substrate on the bottom, the electrically conductive walls on either side and the electrically conductive shield on the top.
It should be noted that a shielded multi-conductor interconnect bus in accordance with the present invention may be fabricated on a substrate that has one or more intervening layers of electrically conductive material and/or dielectric material between the upper surface of the substrate and the first layer of dielectric material. In this regard, the channels in the first dielectric layer extend vertically down into the first dielectric layer to expose the upper surface of an intervening layer of electrically conductive material, and the intervening layer of electrically conductive material, rather than the substrate, serves as the bottom of the equipotential tube.
According to another aspect of the present invention, a method for making a shielded multi-conductor interconnect bus begins with the step of removing portions of a first layer of dielectric material (e.g., a dielectric stack comprising a lower thermal oxide layer and an upper silicon nitride layer) overlying and supported by at least a portion of a substrate (e.g., a silicon substrate) to provide a plurality of substantially parallel channels in the first layer of dielectric material. In this regard, the first dielectric layer may be the lowest layer of material deposited on the substrate and sufficient material may be removed so that th

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