Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2003-08-21
2004-09-21
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S108000, C327S170000, C327S525000, C326S083000, C326S087000
Reexamination Certificate
active
06794909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output circuit of a semiconductor device. In particular, the invention relates to an output circuit of a semiconductor device for outputting an internal signal to the outside.
2. Description of the Background Art
In a system having a plurality of semiconductor devices, a faster interface between the semiconductor devices is desired. For example, in the mobile phone market in which faster, smaller, and larger-capacity memories are required, a plurality of flash memories, static random access memories (SRAMs), and the like are mounted together. In this case, there is a task to stably set switching time between the semiconductor devices to a desired value.
In conventional output circuits of semiconductor devices, a structure having a plurality of CMOS (Complementary Metal-Oxide-Semiconductor) inverters connected in parallel is often used. Although an output circuit having such a structure is designed to have desired circuit characteristics, when variations occur in the characteristics of a MOS transistor during a manufacturing process, there arises a problem that switching time fails to be a desired value.
To solve the foregoing problem, a buffer circuit is proposed in which a fuse portion is provided to each gate of a plurality of P-channel MOS transistors in a PMOS selector circuit connected in parallel with a P-channel MOS transistor, and to each gate of a plurality of N-channel MOS transistors in an NMOS selector circuit connected in parallel with an N-channel MOS transistor. In this case, circuit characteristics of the buffer circuit can be optimized by appropriately cutting the fuse portion to separate part of the plurality of P-channel MOS transistors or N-channel MOS transistors (for example, see Japanese Patent Laying-Open No. 7-38408, which will hereinafter be referred to as a document 1).
There is proposed another buffer circuit having a plurality of CMOS-structure inverter circuits connected in parallel, in which a driving circuit is provided to shut off power supplied to each of a F-channel MOS transistor and an N-channel MOS transistor in at least one of the inverter circuits. A threshold value of the buffer circuit is varied by appropriately changing the number of the respective MOS transistors to be driven (for example, see Japanese Patent Laying-Open No. 5-152930, which will hereinafter be referred to as a document 2).
Further, there is a high-load driving circuit having a plurality of inverters connected in parallel including a P-channel MOS transistor and an N-channel MOS transistor having each gate connected to a fuse. Driving capability of the driving circuit is adjusted by cutting the fuse provided to each inverter as required (for example, see Japanese Patent Laying-Open No. 5-308272, which will hereinafter be referred to as a document 3).
Furthermore, there is an output circuit in which output characteristics of the output circuit are automatically set when an LSI device is operated, by using a monitor circuit having a dummy transistor equivalent to a transistor in the output circuit, and supplying a setting signal to the output circuit based on the result of monitoring a current value of the dummy transistor (for example, see Japanese Patent Laying-Open No. 2000-357956, which will hereinafter be referred to as a document 4).
The present invention aims at optimizing circuit characteristics of an output circuit through a method different from methods proposed in the foregoing documents 1 to 4. In addition, since a semiconductor device has tended to have less tolerance to static electricity in recent years due to a thinner oxide film or the like resulting from miniaturization and higher integration of the semiconductor device, it is necessary to take measures against electrostatic discharge (ESD). However, there is no description about the measures against electrostatic discharge in the methods proposed in the foregoing documents 1 to 4.
SUMMARY OF THE INVENTION
A main object of the present invention is to provide an output circuit of a semiconductor device by which desired circuit characteristics can be obtained and measures against electrostatic discharge can be taken.
An output circuit of a semiconductor device in accordance with the present invention includes an inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type connected between lines of first and second power supply potentials and an output node, respectively, and having input electrodes both receiving an internal signal; a third transistor of the first conductivity type and a first resistor connected in series between the line of the first power supply potential and the output node; and an adjustment circuit including a fuse, for making the third transistor nonconductive when the fuse is not blown, and connecting input electrodes of the first and the third transistors when the fuse is blown, to adjust current driving capability of the output circuit. Therefore, desired circuit characteristics can be obtained by correcting variations in characteristics of MOS transistors caused during a manufacturing process with the adjustment circuit. Further, measures against electrostatic discharge can be taken by providing the resistor between a drain of the third transistor and the output node.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5041738 (1991-08-01), Walters, Jr.
patent: 5821783 (1998-10-01), Torimaru et al.
patent: 5-152930 (1993-06-01), None
patent: 5-308272 (1993-11-01), None
patent: 7-38408 (1995-02-01), None
patent: 2000-357956 (2000-12-01), None
Nakajima Michio
Urakami Aki
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