Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2003-05-06
2004-05-04
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C700S121000, C716S030000
Reexamination Certificate
active
06732062
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to apparatus for analyzing of a semiconductor device; and, more particularly, to an apparatus and a method for analyzing a failure of a semiconductor device on a failure mode basis.
BACKGROUND OF THE INVENTION
As well known, a development of a manufacturing technology of a semiconductor device accelerates a refinement and a high integration of the semiconductor device, and thus, the process or design margin of a manufacturing is decreased. A failure of the semiconductor device is caused by non-uniformity in a wafer such as an error of a mask alignment, an impurity concentration and a thickness of a thin film, or by a minute defect of the wafer. Accordingly, it is required to investigate the causes of the failure of the semiconductor device and improve manufacturing processes of the semiconductor device, so that the production yield can be increased.
A conventional method checks a failure of a semiconductor device on a bit mode of each test mode (i.e., O/S, Function, DC, IDD and the like) by carrying a test device (or a monitor device) such as SRAM into a line at a certain interval (e.g., two weeks), wherein O/S, Function, DC and IDD indicate an open/short test, a signal (pattern) input test, a DC characteristic value test and an electric current characteristic test, respectively.
Such conventional method for analyzing the failure of the semiconductor device automatically calculates a failure die number/rate, a failure bit map (FBM) number/rate, and a good die number/yield on a test mode of a test wafer, as illustrated in FIG.
5
. Herein, FBM represents a rate for a result obtained by checking cell operations of a test device.
Further, the conventional method provides graphs for showing a failure bit mode rate and a failure bit mode number on a failure bit mode of each wafer, as illustrated in
FIGS. 6A and 6B
, respectively. Types of the failure bit mode are represented in right sections of
FIGS. 6A and 6B
.
In other words, the conventional method analyzes and provides information on the failure die number/rate on a test mode, the failure die number/rate on a failure bit mode, the FBM yield, and the die/sorting (D/S) yield.
Meanwhile, when the failure of the semiconductor device is analyzed, it is significant to quickly discover a main cause of failure on the test mode in order to improve the production yield of the semiconductor device. If the failure analysis is focused on the special cause, it is possible to decrease time to achieve a goal of the production yield.
Accordingly, it is required to provide comparison information on each failure bit mode in consideration of an overlap of failure bit modes on the assumption that one die is composed of many units, for example, 128 units. However, said conventional method does not provide such information.
In the conventional method, one die is selected from a test wafer map in order to discover a main failure on a failure bit map and a failure bit mode and check an overlap between the failure bit modes.
Since the main failure is experientially checked or calculated by a handling process in the conventional method, considerable time is required to discover the main failure from the test result. Especially, in case the handling process is used for the calculation, the calculation is not possible because of various overlaps between the failure bit modes. Consequently, the main failure should be experientially checked in the conventional method and errors may occur in checking the main failure, too.
SUMMARY OF THE INVENTION
To solve the problems described above, an embodiment of the present invention provides an apparatus and a method for analyzing a failure of a semiconductor device, which is capable of simply discovering a main failure factor on a failure bit mode basis on a test mode of each wafer.
To solve the problems described above, another embodiment of the present invention provides an apparatus for analyzing a failure of a semiconductor device, which calculates a failure die number/rate, a FBM yield and a D/S yield on a test mode of each test wafer, the apparatus including: a wafer map memory for storing test result data of each test wafer; a means for calculating a failure die number/rate, a D/S good die number/yield and a FBM good die number/yield on the test mode of each test wafer; a means for storing the calculated values; a means for calculating, in case a failure bit mode to be defined is selected from a plurality of failure bit modes, a failure die rate for total dies and a failure die rate for total failure dies based on a total die number and a failure die number of the selected failure bit mode; a means for calculating an expected FBM yield based on the FBM yield and the failure die rate for the total dies and calculating an expected D/S yield based on the expected FBM yield, the FBM yield and the D/S yield; a means for calculating an average D/S yield of the selected failure bit mode based on the expected FBM yield, the FBM yield and the D/S yield of the selected test wafer; a means for calculating a maximum/minimum yield based on the expected FBM yield, and a minimum and a maximum deviation value between the FBM yield and the D/S yield; and a means for displaying the calculated values on a monitor.
To solve the problems described above, still another embodiment of the present invention provides a method for analyzing a failure of a semiconductor device, which calculates a failure die number/rate, a FBM yield and a D/S yield on a test mode of each test wafer, the method including the steps of: (a) calculating a failure die number/rate, a D/S good die number/yield and a FBM good die number/yield on the test mode of each test wafer; (b) waiting for a user to select a failure bit mode to be defined from a plurality of failure bit modes; (c) selecting a certain failure bit mode as a failure bit mode to be defined, and calculating a failure die rate for total dies and a failure die rate for total failure dies based on a total die number and a failure die number of the selected failure bit mode; (d) calculating an expected FBM yield based on the FBM yield and the failure die rate for the total dies; (e) calculating an expected D/S yield based on the expected FBM yield, the FBM yield and the D/S yield; (f) calculating an average D/S yield of the selected failure bit mode based on the expected FBM yield, the FBM yield, and the D/S yield of the selected test wafer; (g) calculating a maximum and a minimum yield based on the expected FBM yield, and a maximum and a minimum deviation value between the FBM yield and the D/S yield; (h) displaying the calculated values on a monitor; and (i) iteratively performing the steps (c) to (h) whenever a new failure bit mode is selected as a failure bit mode to be defined.
REFERENCES:
patent: 5946214 (1999-08-01), Heavlin et al.
patent: 6477685 (2002-11-01), Lovelace
Barlow John
Dongbu Electronics Co. Ltd.
Jacobson & Holman PLLC
Le John
LandOfFree
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