Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-08-16
2004-07-06
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S395420, C709S240000
Reexamination Certificate
active
06760337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to the field of communications, and in particular, to integrated circuits that process communication packets.
2. Statement of the Problem
Communications systems transfer information in packet streams. The packets in the streams each contain a header and a payload. The header contains control information, such as addressing or channel information, that indicate how the packet should be handled. The payload contains the information that is being transferred. Some packets are broken into segments for processing. The term “packet” is intended to include packet segments. Some examples of packets include, Asynchronous Transfer Mode (ATM) cells, Internet Protocol (IP) packets, frame relay packets, Ethernet packets, or some other packet-like information block.
An integrated circuit known as a stream processor has been developed recently to address the special needs of packet communication networking. Traffic stream processors are designed to apply robust functionality to extremely high-speed packet streams. This dual design requirement is often in conflict because the high-speeds limit the level of functionality that can be applied to the packet stream.
Robust functionality is critical with today's diverse but converging communication systems. Stream processors must handle multiple protocols and interwork between streams of different protocols. Stream processors must also ensure that quality-of-service constraints are met with respect to bandwidth and priority. Each stream should receive the bandwidth allocation and priority that is defined in corresponding service level agreements. This functionality must be applied differently to different streams—possibly thousands of different streams.
To provide such functionality, a RISC-based core processor was developed with its own network-oriented instruction set. The instruction set is designed to accomplish common networking tasks in the fewest cycles. The core processor executes software applications built from the instruction set to apply the robust functionality to high-speed packet streams.
A primary task of the core processor is managing a packet transmission schedule. The schedule must attempt to maintain various bandwidth guarantees across multiple streams of traffic. Often, this is implemented through a complex prioritization scheme. For example, real time traffic is a higher priority than non-real time traffic, and e-mail traffic is a higher priority than system back-up traffic. Unfortunately, scheduling of this complex nature requires significant core processing capacity. This use of processing capacity for prioritized scheduling diminishes the level of functionality provided by the stream processor.
SUMMARY OF THE SOLUTION
The invention helps solve the above problems with an integrated circuit that functions as a traffic stream processor. The integrated circuit has a core processor and scheduling circuitry. The scheduling circuitry handles prioritized scheduling for the core processor. The scheduling circuitry reserves packet transmission over various channels using channel specific context. Within a given reservation time period, multiple channels can be reserved at different priority levels. The prioritized scheduling allows the integrated circuit to allocate bandwidth among multiple channels in accord with service level agreements.
The integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards wherein at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets. In some examples of the invention, the scheduling circuitry processes each of the scheduling boards independently of the other scheduling boards.
In some examples of the invention, the scheduling circuitry moves a fence across the time periods on one of the boards at time intervals. The scheduling circuitry initiates packet transmission for one of the reservations at the fence that is at a higher one of the priority levels than the other reservations at the fence. The scheduling circuitry advances the fence at the higher one of the priority levels by one of the time periods at a next one of the time intervals after initiating packet transmission for the one reservation. The scheduling circuitry does not advance the fence for the other reservations at the fence at next one of the time intervals after initiating packet transmission for the one reservation.
In some examples of the invention, the scheduling circuitry comprises a context memory and is configured to associate each scheduling board with a different portion of the context memory. Each scheduling board is separated into time periods at each of the priority levels. The context memory comprises a plurality of entries that each store one of a plurality of channel descriptor indicators. Each of the time periods at each of the priority levels on each of the scheduling boards is associated with a different one of the context memory entries.
In some examples of the invention, the scheduling circuitry sets a first bit in a first one of the time periods at a first one of the priority levels on one of the scheduling boards to schedule packet transmission over a first channel corresponding to a first one of the channel descriptors stored in a first one of the entries associated with the first time period at the first priority level. The scheduling circuitry may set a second bit in the first time period at a second one of the priority levels on the one scheduling board to schedule packet transmission over a second channel corresponding to a second one of the channel descriptors stored in a second one of the entries associated with the first time period at the second priority level. The scheduling circuitry initiates packet transmission for the first time period over the first channel but not the second channel because the first priority level is higher than the second priority level. The scheduling circuitry may set a second bit in a second one of the time periods at a second one of the priority levels on the one scheduling board to schedule packet transmission over a second channel corresponding to a second one of the channel descriptors stored in a second one of the entries associated with the second time period at the second priority level. The scheduling circuitry initiates packet transmission for the first time period over the first channel but not the second channel because the first priority level is higher than the second priority level.
REFERENCES:
patent: 4794526 (1988-12-01), May et al.
patent: 5748630 (1998-05-01), Bergantino et al.
patent: 5920561 (1999-07-01), Daniel et al.
patent: 6208661 (2001-03-01), Marshall
patent: 6418169 (2002-07-01), Datari
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 0 710 046 (1996-01-01), None
Lussier Daniel J.
Snyder II Wilson P.
Tompkins Joseph B.
Conexant Systems Inc.
Hale Kelly H.
Kind Keith
LandOfFree
Integrated circuit that processes communication packets with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit that processes communication packets with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit that processes communication packets with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3230242