Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2002-04-04
2004-07-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S192000, C257S347000, C257S610000, C257S616000
Reexamination Certificate
active
06765227
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor-on-insulator (SOI) integrated circuits and, more particularly, to an SOI wafer having a Si/SiGe/Si active layer and a method of fabricating the SOI wafer using a wafer bonding process.
BACKGROUND ART
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. A silicon active layer is disposed on the BOX layer. Within the active layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by isolation regions. As a result of this arrangement, the active devices are isolated from the substrate by the BOX layer. More specifically, a body region of each SOI transistor does not have body contacts and is therefore “floating.”
SOI chips offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). In such circuits, dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and the packing density greatly increased.
However, the mobility of the carriers (i.e., electrons or holes) within the silicon of the active layer, and primarily in a channel portion of the body region, is limited. Therefore, there exists a need in the art to increase the mobility of the carriers within the channel of SOI devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer.
According to another aspect of the invention, the invention is a semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate; a buried oxide (BOX) layer disposed on the substrate; and an active layer disposed on the BOX layer, the active layer having an upper silicon layer disposed on a silicon-germanium layer, the silicon-germanium layer disposed on a lower silicon layer, wherein the silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.
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Quinones et al, “Design, Fabrication, and Analysis of SiGeC Hetrojunction of PMOSFETs” IEEE trans. on electronic devices vol. 47, No. 9, Sep. 2000.
An Judy Xilin
En William G.
Riccobene Concetta E.
Yu Bin
Advanced Micro Devices , Inc.
Flynn Nathan J.
Renner , Otto, Boisselle & Sklar, LLP
Sefer Ahmed N.
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