Non-volatile semiconductor memory

Details Non-volatile semiconductor memory Non-volatile semiconductor memory

2002-09-12

2004-03-09

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S185170, C365S185280, C365S185290

Reexamination Certificate

active

06704223

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile memory.
Large-scale integrated semiconductor memories are provided with redundant circuitry for remedying defectiveness. The same is applied to electrically-erasable (rewritable) non-volatile memories (EEPROM).
Well-known redundant circuitry has redundant raw and column cell arrays to a memory cell array and a fuse circuit for storing addresses at which defective memory cells are located (called defective addresses hereinafter). Such a fuse circuit mostly consists of laser-brown type fuses.
Defective addresses for defective cells detected in a wafer test are programmed onto a fuse circuit. Once the fuse circuit has been programmed, an input detective address is compared with the defective addresses stored in the fuse circuit. If they are met, a replacement control is performed such that a decoder is controlled to select a redundant cell in place of the defective cell.
In addition to storing address data for a remedy for defectiveness as described above, the fuse circuit stores several initially-setting data for deciding memory operation requirements. The initially-setting data includes adjustment data to chip internal voltages that vary among chips or wafers, setting data for data-programming voltage, control parameters for the number of loops for programming (writing) and erasing, and so on.
The fuse circuit, however, cannot be reprogrammed. Moreover, defective cell detection by a tester in a wafer test and laser-fuse blowing are different processes so that they cannot be performed as a sequential process.
In place of such a fuse circuit, an electrically-erasable non-volatile memory cell the same as a memory cell for an EEPROM has been proposed as an initially-setting data storing circuit because such a non-volatile memory cell can easily program data compared to a fuse blowing and is data-rewritable.
However, proposed so far is a system in which a non-volatile memory cell array for storing initially-setting data is provided separately from a data-storing memory cell array. Such a system thus requires circuitry specially for reading data from, programming data to and erasing data in a memory cell array for storing initially-setting data other than that for a data-storing memory cell array. This results in complex circuitry, increase in chip area and also complex control for data verification and reprogramming, etc.
SUMMARY OF THE INVENTION
A purpose of the present invention is to provide a non-volatile memory cell capable of storing initially-setting data with easy data verification and reprogramming.
The present invention provides a non-volatile semiconductor memory including; a memory cell array having a plurality of electrically-rewritable non-volatile memory cells, provided with an initially-setting data area, written in which is initially-setting data for deciding memory operation requirements; a first decoder that selects memory cells in the memory cell array according to address signals; a sense-amplifier that detects and amplifies data stored in at least a memory cell selected by the first decoder; a latch circuit having a plurality of initially-setting data latches that latches the initially-setting data: and a controller that reads out the initially-setting data via the first decoder and the sense-amplifier and transfers the initially-setting data to the latch circuit.
According to the invention, initially-setting data is written (programmed) in an initially-setting data area of a memory cell array. The initially-setting data can be read out by a decoder and a sense-amplifier, like in usual data reading.
A controller used for writing (programming) and erasing control is preprogrammed so as to automatically execute an initially-setting operation to read out initially-setting data written in the initially-setting data area of a memory cell and transfer the data to an initially-setting data latch after power is on.
Accordingly, the present invention does not require any special circuitry for storing initially-setting data in an area apart from the memory cell array.
The decoder and the sense-amplifier can be shared by both usual data reading and initially-setting data reading, thus the present invention achieves simple circuitry on a small chip area.
The present invention also offers easy verification and updating of initially-setting data.


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patent: 5523974 (1996-06-01), Hirano et al.
patent: 6052313 (2000-04-01), Atsumi et al.
patent: 08-044628 (1996-02-01), None
patent: 2000-112826 (2000-04-01), None

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