Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-04-13
2004-04-13
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S632000, C257S741000, C257S750000, C257S758000, C257S765000
Reexamination Certificate
active
06720660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
Typically, a semiconductor device includes a semiconductor substrate, and an electronic element and a wiring that are formed over the main surface of the semiconductor substrate. The semiconductor device may include an interlayer dielectric film. A silicon oxide film is widely used as the interlayer dielectric film. A variety of methods are available for forming a silicon oxide film. For example, a silicon oxide film may be formed by reacting a silicon compound such as silane or the like with hydrogen peroxide by a CVD method (hereinafter referred to as “planarizing silicon oxide film”). For example, this method is described in Japanese Laid-open Patent Application HEI 9-102492. The planarizing silicon oxide film has an excellent planarization characteristic.
An interlayer dielectric film that includes a planarizing silicon oxide film may have variations in film thickness depending on locations on the main surface of the semiconductor substrate. For example, the variations occur due to the following reasons.
First, the main surface of the semiconductor substrate includes a region where wirings are formed with a high wiring density and a region wherein wirings are formed with a low wiring density. The thickness of the planarizing silicon oxide film formed over the high wiring density region is generally greater than the thickness of the planarizing silicon oxide film formed over the low wiring density region, due to a high level of flowability of the planarizing silicon oxide film.
Secondly, as the number of wiring layers increases, the number of interlayer dielectric films typically increases. Each interlayer dielectric film has variations in thickness. Such thickness variations in a plurality of the interlayer dielectric films may add up where the interlayer dielectric films overlap one another. As a result, the added thickness variation becomes greater at an upper level than at a lower level of the interlayer dielectric films. As the thickness variation becomes greater, a step difference in an interlayer dielectric film becomes larger.
When a through hole is formed in an interlayer dielectric film, a resist is used. A focus margin in exposure with respect to the resist becomes smaller when the step difference in the interlayer dielectric film becomes larger. As a result, the resolution at the resist lowers. As a consequence, a designed shape of a through hole may not be formed, or in the worst case, a through hole may not be formed at all.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a method for manufacturing a semiconductor device having a structure in which a focus margin does not become smaller.
A semiconductor device in accordance with one embodiment of the present invention has a semiconductor substrate having a main surface including a first region and a second region, and an interlayer dielectric film formed over the first region and the second region. In accordance with one embodiment of the present invention, for example, at least a bonding pad, a power source line, a test pattern or the like is formed in the first region. Also, in accordance with one embodiment of the present invention, at least a logic circuit, an analog circuit, a memory circuit or the like is formed in the second region.
The interlayer dielectric film defines a first through hole over the first region and a second through hole over the second region. In a preferred embodiment, the interlayer dielectric film has a maximum thickness over the first region. The interlayer dielectric film over the second region has a thickness that is about 90-50% of the maximum thickness. More preferably, the interlayer dielectric film over the second region has a thickness that is about 80-50% of the maximum thickness. In a preferred embodiment, an aperture area of the first through hole is greater than that of the second through hole.
It is noted that the problem of reduced focus margin is substantially eliminated when he film thickness over the second region is greater than about 90% of a maximum film thickness over the first region. When the film thickness over the second region is smaller than about 50%, the capacitance between metal wirings (such as for example, aluminum wirings) becomes large. As a result, the electrical characteristics of the semiconductor device deteriorate. Also, when a difference in the film thickness of the interlayer dielectric film becomes larger, an etching operation to form through holes becomes more difficult.
In a semiconductor device in accordance with one embodiment of the present invention, an aperture area of the first through hole is greater than an aperture area of the second through hole. As a result, a resist can be exposed with a focus margin for forming the second through hole. Thus, the focus margin does not become too small. The details will be described below with reference to preferred embodiments of the present invention.
In a semiconductor device in accordance with the present invention, a member that reduces the volume of the first through hole may preferably be formed in the first through hole due at least in part to the following reasons. An aperture area of the first through hole is greater than an aperture area of the second through hole. Accordingly, the first through hole has a greater volume than that of the second through hole. When conductive films are formed in the first and second through holes, the amount of the conductive film may not be sufficient to fill the first through hole, and there is a likelihood that the conductive film formed in the first through hole may have a recess. The recess results in a step difference in the interlayer dielectric film. The member formed in the first through hole can solve such problems as described above.
In one embodiment, the member may be formed as follows. The first through hole is formed by etching the interlayer dielectric film in a manner that the interlayer dielectric film in a column form remains at a center of the first through hole. The remaining column-like interlayer dielectric film occupies the internal space of the first through hole to serve as a member,
In accordance with one embodiment of the present invention, a semiconductor device may be manufactured by the following method. A semiconductor device formed by a manufacturing method in accordance with the embodiment of the present invention has a semiconductor substrate having a main surface including a first region and a second region, and an interlayer dielectric film formed over the first region and the second region. The interlayer dielectric film defines a first through hole over the first region and a second through hole over the second region. The manufacturing method includes the following steps:
(a) The interlayer dielectric film is formed over the first region and the second region, wherein the interlayer dielectric film has a maximum thickness over the first region, and the interlayer dielectric film has a thickness that is 90-50% of the maximum thickness over the second region;
(b) A resist is formed over the interlayer dielectric film;
(c) The resist is exposed to light to form a pattern in the resist, wherein the resist pattern has an aperture for the first through hole and an aperture for the second through hole, wherein an area of the aperture for the first through hole is greater than an area of the aperture for the second through hole; and
(d) The first through hole and the second through hole are formed by selectively etching the interlayer dielectric film using the resist as a mask.
The exposure in step (c) is conducted by, for example, one of a reduction projection exposure, an equal magnification (1:1) projection exposure and a scanning-type reduction projection exposure.
In a semiconductor device in accordance with one embodiment of the present invention, the interlayer dielectric film may
Eckert George
Hogan & Hartson LLP
Richards N. Drew
Seiko Epson Corporation
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