Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2001-06-21
2004-03-09
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
Reexamination Certificate
active
06703650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor integrated circuit, such as a gate array or an embedded array, and more specifically, it relates to a semiconductor integrated circuit having a circuit which protects against static electricity.
2. Description of Related Art
A semiconductor integrated circuit, such as a gate array or an embedded array, often incorporates power supply cells in input/output cell areas.
FIG. 5
is a schematic view of a conventional semiconductor integrated circuit which includes such input/output cell areas. As shown in
FIG. 5
, a V
DD
cell incorporating a V
DD
terminal to which a high-potential supply voltage V
DD
is applied, and a V
SS
cell incorporating a V
SS
terminal to which a low-potential supply voltage V
SS
is applied, are arranged as power supply cells. Conventionally, the V
SS
cell is connected such that the power supply is directly transmitted from the V
SS
terminal to an inner cell area (PATH 1). The V
DD
cell has an electrostatic protection circuit (diode) formed between the V
DD
and the V
SS
, so that when static electricity is applied to a power supply terminal, the static electricity may be discharged to the outside via the electrostatic protection circuit (PATH 2).
The reason that this electrostatic protection circuit is provided is described hereinbelow. For example, static electricity, which is charged on a living body, has a positive charge, and when static electricity having a positive charge is applied to the V
SS
terminal as the living body touches the semiconductor integrated circuit, a reverse voltage is generated between the V
DD
terminal and the V
SS
terminal, possibly resulting in damage to transistors in the inner cell. Thus, the electrostatic protection circuit described above is often provided in a typical power supply cell.
However, when static electricity having an excessive voltage is applied to the V
SS
terminal, the static electricity is transmitted to the inner cell directly connected to the V
SS
terminal before the static electricity is discharged to the outside via the electrostatic protection circuit. This may cause electrostatic destruction of the inner cell.
SUMMARY OF THE INVENTION
Accordingly, in view of the foregoing points, it is an object of the present invention to provide a semiconductor integrated circuit in which, even if excessive static electricity is applied to a V
SS
cell, the static electricity is discharged to the outside via an electrostatic protection circuit before the static electricity is transmitted to an inner cell to prevent electrostatic destruction of the inner cell.
In order to solve the above problems, a semiconductor integrated circuit according to the present invention includes a plurality of input/output cells including a high-potential power supply cell incorporating a high-potential power supply terminal, and a low-potential power supply cell incorporating a low-potential power supply terminal. A first lower wiring layer has a plurality of wires connected to the high-potential power supply terminal and the low-potential power supply terminal. At least one higher wiring layer is formed over the lower wiring layer across an insulating interlayer, and is electrically connected to the lower wiring layer via a hole provided in the insulating interlayer. A protection diode has a cathode and an anode electrically connected to the high-potential power supply terminal and the low-potential power supply terminal, respectively, via at least the lower wiring layer. An inner cell is electrically connected to the high-potential power supply terminal and the low-potential power supply via both the lower wiring layer and the higher wiring layer.
Furthermore, the inner cell may be electrically connected to the low-potential power supply terminal via a lower wiring layer located on the low-potential power supply cell, the higher wiring layer, and a lower wiring layer located on an input/output cell other than the low-potential power supply cell.
According to the present invention, the current from a V
SS
terminal is bypassed once to a higher wiring layer, so that even if static electricity having an excessive voltage is applied to a V
SS
cell, the static electricity can be discharged to the outside via an electrostatic protection circuit before the static electricity is transmitted to an inner cell, which prevents electrostatic destruction of the inner cell.
REFERENCES:
patent: 6060752 (2000-05-01), Williams
patent: 6339234 (2002-01-01), Takizawa
patent: 62-224043 (1987-10-01), None
patent: 04-061371 (1992-02-01), None
patent: 06-224372 (1994-08-01), None
Ito Satoshi
Seki Hiroshi
Nguyen Cuong Quang
Oliff & Berrdge, PLC
Seiko Epson Corporation
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