Multi-bank chip compatible with a controller designed for a...

Details Multi-bank chip compatible with a controller designed for a... Multi-bank chip compatible with a controller designed for a...

2003-06-11

2004-01-06

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080, C365S230060, C365S230020

Reexamination Certificate

active

06674684

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a multi-bank memory chip that can operate with a controller designed for controlling a chip having a lesser number of banks and a method of operating such a chip.
BACKGROUND OF THE INVENTION
Use of Dynamic Random Access Memory (DRAM) chips is well known in the computer field. Each memory chip contains at least one bank of a plurality of memory cells arranged in a row and column array. Each cell can contain a number of data bits. As memory technology has advanced, the capacity of chips has increased. For example, present day Synchronous DRAM (SDRAM) memory chips have a plurality of internal banks of the memory cells, for example, four or eight, with each bank having the row and column array of the memory cells. An individual cell of a memory bank of a multi-bank chip is addressed for purposes of reading or writing data by first selecting the memory bank and then addressing the row and column of the cell in the selected bank. The addressing is accomplished by a memory controller external of the chip that is often located on a computer system board, such as the mother board of a personal computer.
SDRAM chip internal banks of memory are separate entities. This allows the memory controller to operate multiple read/write requests at the same time with each request addressing a selected bank. When addressing a memory cell of a particular memory bank of the chip, the memory controller must produce bank identification, “bank ID”, bits with each memory command/address so that the chip will know the memory bank for which the address and commands are intended.
An SDRAM chip has an on-chip mode register which is programmed by the external controller with the bank selection (bank ID) bits and the cell address and commands. The set of address/command bits supplied to the chip mode register is often referred to as a “Mode Register Set” (MRS). The details of the MRS bits, such as read and write commands, burst length and burst type used to execute various functions for different types of chips, such as DRAMs, is well known in the art and only the chip functions needed to describe the invention are presented here.
As an example to aid in the explanation of the invention, consider a chip of 1 Gb capacity that has four memory banks. To read data from a memory cell of one bank of the chip, two commands are needed. The format of the command and address of the chip MRS is represented as follows:
CHART A
Function
CKE
CS
RAS
CAS
WE
BA0
A15-A11
A10
A9-A0
BA1
Bank Active
H
L
L
H
H
Bank
Row Address
Address
Read with Auto
H
L
H
L
H
Bank
Column
H
Column
Pre-charge
Address
Address
Address
The legends used in the Chart above, which are relatively conventional, are explained below together with other explanatory material relative to the particular chip being considered.
CKE—activates the system CLK (clock) signal when high (H) and deactivates the CLK signal when low (L). This can be used to initiate either a Power Down mode, Suspend mode or Self Refresh mode.
CS—enables the command decoder when low (L) and disables the command decoder when high (H). When the command decoder is disabled, new commands are ignored but previous operations continue.
A
0
-A
15
—the bits of the address bus. SDRAM breaks down the memory array address into ROW and Column addresses, and these addresses are sent by multiplex ROW and Column address at different times on the address bus. For example, a 512 Mb chip will have bits A
0
-A
13
for ROW address bits and A
0
-A
9
, A
11
for Column address bits.
RAS—row address select. During a Bank Active command cycle, Address bits A
0
-A
12
define the row address (RA
0
-RA
12
) when sampled at the rising clock edge.
CAS—column address select. Bits A
0
-A
9
and A
11
-A
15
. The number of bits of the Column address depends upon the number of memory cells activated by the Row address bits. As conventional, as the capacity of DRAM chips becomes larger, the size of each row stays relatively constant due to memory power consideration. Therefore, the column address usually has fewer bits than a ROW address.
WE—write enable. When active, indicates the write operation to the Column memory cell addressed.
BA—bank address field. A four bank DRAM chip MRS has two bank ID bits BA
0
, BA
1
to select to which of the four banks a command applies. An eight bank chip would have three bank ID bits BA
0
, BA
1
, BA
2
.
A
10
(=AP)—is used to invoke the autoprecharge operation at the end of the burst read or write cycle. If A
10
is high, autoprecharge is selected and the bank ID bits BA
0
, BA
1
define the bank to be precharged. If A
10
is low, autoprecharge is disabled. During a precharge command cycle, A
10
(=AP) is used in conjunction with the bank ID bits BA
0
and BA
1
to control which bank(s) to precharge. If A
10
is high, all four banks will be precharged regardless of the state of BA
0
and BA
1
. If A
10
is low, then BA
0
and BA
1
are used to define which bank to precharge.
FIG. 1
shows part of a typical four bank chip
10
, such as found in a DDR2 512 Mb chip. Only the parts of the chip address logic and circuits pertinent to the invention are shown. The read and write functions are standard and are omitted. The chip
10
is operated by an external controller
60
. Chip
10
has four memory banks,
12
-
0
,
12
-
1
,
12
-
2
and
12
-
3
, each bank having a plurality of memory cells arranged in rows and columns. The cell of a memory bank
12
is addressed by instructions supplied by an external controller
60
. That is, the controller
60
is not part of the chip and is typically located in another part of the computer in which the chip
10
is being used. Each memory bank
12
has corresponding sense amplifiers
13
and outputs to an input/output (I/O) gating mask logic circuit
15
. All of this is conventional.
The controller
60
produces instructions for only two bank ID bits, BA
0
and BA
1
. Thus, it is designed to operate with a chip in which there are no more than four memory banks
12
. Signals, such as those referred to in Chart A above, are applied as instructions from the external controller
60
to a chip control logic circuit
20
that includes a command decoder
22
that decodes the instructions from the controller
60
. There is also an address register
30
to which the address bits A
0
-A
12
and the two bank ID bits BA
0
and BA
1
are input and stored.
The bank select ID bits BA
0
and BA
1
from the address register
30
are applied to a bank control logic circuit
34
to determine which of the four banks
12
-
0
,
12
-
1
,
12
-
2
and
12
-
3
is to be selected for a read or write operation. Depending upon which one of the four banks that is selected, a corresponding bank row decoder
40
-
1
,
40
-
1
,
40
-
2
and
40
-
3
, as well as a corresponding bank column decoder
42
-
0
,
42
-
1
,
42
-
2
and
42
-
3
also is selected. To address a memory cell of the selected bank
12
-
0
to
12
-
3
, the RAS (row address select) address bits A
0
-A
12
are appropriately applied to a row address multiplexer
44
. Next, the CAS (column address select) bits A
0
-A
9
, A
11
and A
12
are applied to a column address counter and latch circuit
46
. There is also a refresh circuit
48
that recharges the chip memory cell transistors (at AP=A
10
). Read and write operations are performed on the selected cell of a bank by selecting one of the four banks
12
-
0
to
12
-
3
by using the two bank ID bits BA
0
, BA
1
and the column and row addresses.
Charts B1 and B2 show certain of the details of two different size chips. Chart B1 illustrates a four bank 512 Mb chip with the bank ID bits BA
0
and BA
1
. The autoprecharge occurs at A
10
, with the row address RAS being from A
0
-A
13
and the column address CAS being at A
0
-A
9
, A
11
. Chart B2 illustrates a four bank chip of 1 Gb capacity. Therefore, it has one additional bit A
0
-A
14
for the row address.
512 Mb Chart B1
Configuration
128 Mb × 4
# of Banks
4
Bank ID
BA0, BA1
Auto precharge
A
10
/AP
Row Address
A
0
-A
13
Column Address
A
0
-A
9

Affiliated with

Also associated with

Rating

Multi-bank chip compatible with a controller designed for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-bank chip compatible with a controller designed for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-bank chip compatible with a controller designed for a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3227058