Semiconductor memory device having potential control circuit

Details Semiconductor memory device having potential control circuit Semiconductor memory device having potential control circuit

2002-08-19

2004-04-06

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S226000, C365S185110

Reexamination Certificate

active

06717881

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of conductive lines in a memory cell array connected to a plurality of memory cells arranged in two adjacent column directions, respectively.
2. Description of the Background Art
Attention is paid to an NROM (Nitride Read Only Memory) type flash EEPROM (to be referred to as “NROM” hereinafter) which is a kind of a flash EEPROM among nonvolatile semiconductor memory devices. NROM is reported in U.S. Pat. Nos. 6,011,725 and 6,201,737.
FIG. 23
is a circuit diagram showing the configuration of the memory cell array of a conventional nonvolatile semiconductor memory device.
Referring to
FIG. 23
, the memory cell array includes a plurality of nonvolatile memory cells MC, a plurality of bit lines BL and a plurality of word lines WL.
Plural word lines WL and plural bit lines BL are arranged in row and column directions, respectively.
Each of plural nonvolatile memory cells MC is arranged to correspond to the intersection between word line WL and bit lie BL. Plural nonvolatile memory cells MC arranged in the same row are connected in series and the gates thereof are connected to same word line WL. Each bit line BL is arranged to pass through the connection point between two adjacent nonvolatile memory cells MC.
Nonvolatile memory cell MC includes two storage regions L
1
and L
2
.
Data write and read operations for wiring and reading data to and from storage regions L
1
and L
2
of nonvolatile memory cell MC will next be described.
FIGS. 24A
to
24
D are views showing the data write or read operation for writing or reading data to and from the two storage regions in nonvolatile memory cell MC.
Referring to
FIG. 24A
, the gate of nonvolatile memory cell MC is connected to word line WL. Nonvolatile memory cell MC is assumed to be connected to bit lines BL
0
and BL
1
. Nonvolatile memory cell MC has storage region L
1
on a bit line BL
0
side and storage region L
2
on a bit line BL
1
side as shown in FIG.
24
C.
The write operation for writing data to storage region L
1
will first be described. Referring to
FIG. 24A
, if data is to be written to storage region L
1
, the potential of bit line BL
0
is kept to be a write potential VCCW and that of bit line BL
1
is kept to be a ground potential GND. As a result, a write current Ifw is carried from bit line BL
0
to bit line BL
1
through nonvolatile memory cell MC. At this moment, data is written to storage region L
1
. Such a write operation for writing data to storage region L
1
in nonvolatile memory cell MC will be referred to as “forward write”.
Next, the read operation for reading data from storage region L
1
will be described. Referring to
FIG. 24B
, if data is to be read from storage region L
1
, the potential of bit line BL
0
is kept to be ground potential GND and that of bit line BL
1
is kept to be read potential VCCR. As a result, a read current Ifr is carried from bit line BL
1
to bit line BL
0
. At this moment, data is read from storage region L
1
. Such a read operation for reading data from storage region L
1
in nonvolatile memory cell MC will be referred to as “forward read”.
As can be seen, the direction of the current flowing during the write operation is opposite to that of the current flowing during the read operation in storage region L
1
.
The write operation for writing data to storage region L
2
will next be described. Referring to
FIG. 24C
, if data is to be written to storage region L
2
, the potential of bit line BL
0
is kept to be ground potential GND and that of bit line BL
1
is kept to be write potential VCCW. As a result, a write current Irw is carried from bit line BL
1
to bit line BL
0
. At this moment, data is written to storage region L
2
. Such a write operation for writing data to storage region L
2
in nonvolatile memory cell MC will be referred to as “reverse write”.
Next, the read operation for reading data from storage region L
2
will be described. Referring to
FIG. 24D
, if data is to be read from storage region L
2
, the potential of bit line BL
0
is kept to be read potential VCCR and that of bit line BL
1
is kept to be ground potential GND. As a result, a read current Irr is carried from bit line BL
0
to bit line BL
1
. At this moment, data is read from storage region L
2
. Such a read operation for reading data from storage region L
2
in nonvolatile memory cell MC will be referred to as “reverse read”.
As can be seen, the direction of the current flowing during the write operation is opposite to that of the current flowing during the read operation in storage region L
2
as in the case of storage region L
1
. Further, the direction of the current flowing during the write operation for writing data to storage region L
1
is opposite to that of the current flowing during the write operation for writing data to storage region L
2
. Likewise, the direction of the current during the read operation for reading data from storage region L
1
is opposite to that of the current flowing during the read operation for reading data from storage region L
2
.
Therefore, it is important to control the potentials of respective bit lines BL during the write operation of NROM.
However, U.S. Pat. Nos. 6,011,725 and 6,201,737 fail to describe the peripheral circuits of a memory cell array which control the potentials of respective bit lines BL.
In addition, in flash EEPROM represented by NROM, the bit lines are formed, as diffused bit lines, on the main surface of a semiconductor substrate.
FIG. 25
is a plan view of conventional flash EEPROM.
Referring to
FIG. 25
, the nonvolatile semiconductor memory device has a plurality of bit lines BL arranged in a column direction. Plural bit lines BL are diffused bit lines formed on the main surface of the semiconductor substrate. Plural word lines WL are arranged in a row direction on plural bit lines BL. A plurality of metal wirings ML are arranged in the column direction on plural word lines WL. Plural metal wirings ML are arranged to correspond to plural bit lines BL, respectively and corresponding metal wiring ML and bit line BL are connected to each other through a plurality of contact sections
20
.
FIG. 26
is a cross-sectional view taken along line XXVI—XXVI of FIG.
25
.
Referring to
FIG. 26
, an n type diffused region
22
is formed on the main surface of a semiconductor substrate
21
. This n type diffused region
22
corresponds to bit line BL shown in FIG.
25
.
On the main surface of semiconductor substrate
21
, insulating films
23
a
to
23
d
are formed at predetermined intervals. A word line WL
1
is formed on insulating film
23
a
. A word line WL
2
is formed on insulating film
23
b
. A word line WL
3
is formed on insulating film
23
c
. A word line WL
4
is formed on insulating film
23
d
. Word lines WL
1
to WL
4
are formed out of, for example, silicon.
On the main surface of semiconductor substrate
21
, an interlayer insulating film
24
is formed in a region located on n type diffused region
22
on word lines WL
1
to WL
4
on the main surface of semiconductor substrate
21
. Metal wiring ML is formed on interlayer insulating film
24
.
Contact holes
25
a
and
25
b
are formed in a region located between insulating films
23
b
and
23
c
on n type diffused region
22
. The surface of n type diffused region
22
is exposed to the bottom of each of contact holes
25
a
and
25
b
. Metal wiring ML is extended to the respective bottoms of contact holes
25
a
and
25
b
and connected to n type diffused region
22
.
FIG. 27
is an explanatory view for a write operation for writing data to a nonvolatile memory cell in the memory cell array shown in FIG.
23
.
Referring to
FIG. 27
, a case where H-level data is written to storage region L
1
of a nonvolatile memory cell MC
1
shown therein will be described.
Word line WL
1
is selected, the potential of bit line BL
0
is kept to write potential VCCW and that of bit lie BL
2
is k

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