Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-10-24
2004-09-14
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S541000
Reexamination Certificate
active
06791396
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to circuitry for memory cell arrays, such as circuitry that may be used for voltage regulators for erasable, programmable read only memories (EPROMs), electrically erasable, programmable read only memories (EEPROMs), and flash EEPROM memories, for example.
BACKGROUND OF THE INVENTION
Voltage regulators are circuits useful for providing accurate analog voltages for erasable, programmable read only memories (EPROMs) and other integrated circuits. A voltage regulator may typically comprise a reference voltage, a comparator, a driver and a resistor divider. An example of a prior art voltage regulator is shown in
FIG. 1
, and uses a so-called Miller architecture, well known in the art. A comparator GM
1
is connected to the gate of a PMOS (p-channel metal oxide semiconductor) driver GM
2
. The comparator GM
1
is supplied a supply voltage V
PP
, and compares voltages IP and FB. The comparator GMI adjusts the gate voltage of the PMOS driver GM
2
to equalize voltages IP and FB. The output voltage, OP, is thus a multiple of the input voltage, IP. The multiplication factor is determined by the resistor divider (RD) ratio between OP and FB.
A problem with this type of regulator is that a large current (typically >100 &mgr;A) is required across the resistor divider RD in order to establish the multiplication factor. It is possible to make this current arbitrarily small by increasing the resistance of the divider. However, this may have several undesirable effects. First, the drive capability of the regulator may be lowered. Second, increasing the resistance may require significant silicon area. Third, the speed of the feedback is a function of the current, and as such, lowering the current may substantially degrade the regulator's stability.
In EPROM applications, the V
PP
supply (
FIG. 1
) is usually a pumped voltage. Pumping from the chip supply (V
DD
) to a higher voltage (V
PP
) is a process that has a low efficiency. Any current consumption from V
PP
requires a significantly larger current consumption from V
DD
, usually by a factor of 5-10. As such, it is critical to conserve current in regulators operating from a boosted source, such as those providing the wordline voltage in EPROMs. In the regulator of
FIG. 1
, the resistor divider drains current from the V
PP
supply, such that a current of 100 &mgr;A required across the resistor divider may mean a V
DD
current of 1 mA.
Accordingly, there is a need for a regulator that has a low current consumption from V
PP
or another supply, while providing a high drive capability.
SUMMARY OF THE INVENTION
The present invention seeks to provide a stack element circuit that may be used to provide an improved voltage regulator. The present invention may comprise stacked diode-connected transistors that receive a reference current or a multiple thereof from a reference element, which may be a reference transistor. Diode-connected transistors are transistors whose gate is connected to the drain. The diode-connected transistors and the reference element are preferably matched such that a gate-source voltage of the diode-connected transistors is generally the same as the gate-source voltage of the reference element.
There is thus provided in accordance with a preferred embodiment of the present invention a circuit including a reference element adapted to provide a reference current and having a control terminal and a first terminal, there being a voltage (V
ct
) between the control terminal and the first terminal of the reference element, and a plurality of series-connected stack elements, each the stack element including a first terminal connected to a first voltage, and a control terminal connected to a second terminal, the stack elements being adapted to receive at least one of the reference current and a multiple of the reference current, the stack elements and the reference element being matched such that a voltage between the control terminal and the first terminal of at least one of the stack elements is generally the same as V
ct
.
In accordance with a preferred embodiment of the present invention a voltage between the control terminal and the first terminal of each the stack element is generally the same as V
ct
.
Further in accordance with a preferred embodiment of the present invention one of the first and second terminals comprises an input and the other of the first and second terminals comprises an output, and the output of a first stack element is connected to the input of a subsequent stack element.
Still further in accordance with a preferred embodiment of the present invention the reference element is at a voltage V
DD
and the stack elements are at voltage V
PP
wherein V
PP
≧V
DD
.
In accordance with a preferred embodiment of the present invention the stack elements include diode-connected transistors and the reference element includes a transistor, the diode-connected transistors and the reference element being matched such that a gate-source voltage of the diode-connected transistors is generally the same as V
ct
.
Further in accordance with a preferred embodiment of the present invention the reference element is adapted to have a fixed V
ct
voltage.
Still further in accordance with a preferred embodiment of the present invention the circuit includes a voltage regulator having an input and an output, wherein the input is a control terminal of the reference element, and the output is an output of a top transistor of the stack, the top transistor being the first of the diode-connected transistors that receives the reference current.
In accordance with a preferred embodiment of the present invention the first terminal includes an input and the second terminal includes an output.
In accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS (n-channel metal oxide semiconductor) transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain.
Further in accordance with a preferred embodiment of the present invention the reference element receives a reference voltage at the control terminal and the output generates the reference current.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, wherein for each NMOS transistor, a resistor is connected between a source of the transistor and the first terminal, a bulk of the transistor is connected to at least one of the source and the first terminal, the control terminal includes a gate, the first terminal comprises an input of the stack element and the second terminal includes an output including a drain.
Additionally in accordance with a preferred embodiment of the present invention an input of the reference element is at ground (GND).
In accordance with a preferred embodiment of the present invention an output of the circuit is the output of the top stack element, the top stack element being the first of the stack elements that receives the reference current.
Further in accordance with a preferred embodiment of the present invention a bottom stack element, the bottom stack element being the last of the stack elements that receives the reference current, receives a second reference voltage at its input.
Still further in accordance with a preferred embodiment of the present invention the stack elements and the reference element include NMOS transistors, and the first terminal includes an input including at least one of a source and bulk, the control terminal includes a gate, and the second terminal includes an output including a drain, wherein the reference element receives a reference voltage at the control terminal and the output generates the reference current, wherein an input of the reference element is at ground (GND), wherein an output of the circuit is the output of the top stack element, the top stack elemen
Maayan Eduardo
Shor Joseph S.
Cunningham Terry D.
Eitan, Pearl, Latzer & Cohen Zedek LLP
Saifun Semiconductors Ltd.
Tra Quan
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