High speed voltage level shifter

Details High speed voltage level shifter High speed voltage level shifter

2002-02-07

2004-01-13

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C326S068000, C326S081000, C327S536000

Reexamination Certificate

active

06677798

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, in particular, to a high speed voltage level shifter.
BACKGROUND OF THE INVENTION
With the introduction of integrated circuits with geometry below 0.13 &mgr;m, lower power supply voltages have become necessary to maintain device reliability. Consequently, supply voltage has decreased from 3.3 volts to 1.2 volts or less. However, many interface signals still use the logic level from 0 to 3.3 or 5 volts. The circuitry therefore can be divided into “core” circuits and I/O circuits, where the core logic operates at the lower 1.2 volts, and the I/O circuits operate at 3.3 volts. To interface between circuits requiring different voltage levels, a voltage level shifter is employed to switch between the voltage levels of the respective circuits.
FIG. 1
shows a well-known circuit implementation of a voltage level shifter
100
. A NMOS transistor MN
1
has its gate connected to a core circuit supply voltage (V
CCL
). Both PMOS transistors MP
1
, MP
2
have their sources connected to an I/O voltage source V
CCH
, which has a higher voltage potential than V
CCL
. The level shifter
100
translates a low voltage input signal at an input terminal
110
to a high voltage output signal at an output terminal
130
. For such a voltage level shifter to operate properly, the PMOS transistor MP
1
is “weak” compared to the transistors MN
1
, MN
2
and MP
2
.
With continued reference to
FIG. 1
, when the input signal is logic low, the NMOS transistor MN
2
is “on” via an inverter
120
. As a result, the NMOS transistor MN
2
electrically drives the output terminal
130
to ground. Further, the logic low output signal turns “on” the PMOS transistor MP
1
which provides the supply voltage V
CCH
to a gate of the PMOS transistor MP
2
, thereby the PMOS transistor MP
2
is held “off”.
When the input signal goes high, the NMOS transistor MN
2
is turned “off”. The NMOS transistor MN
1
electrically connects the gate of the PMOS transistor MP
2
to an inverted input signal at logic low (i.e., ground). Hence, the PMOS transistor MP
2
is turned “on” and provides the supply voltage V
CCH
to the output terminal
130
.
The voltage level shifter
100
is suitable for ordinary applications. However, when the supply voltage V
CCL
approaches 1.2 volts or less, the NMOS transistors in the level shifter
100
cannot be conducted sufficiently due to a typical threshold voltage of 0.8 volts. The gate voltage that brings about conduction in a transistor is called the threshold voltage. In the case of an input signal having a voltage swing between 0 and 1.2 volts, an output signal at the output terminal
130
should be logic low when the gate of the NMOS transistor MN
2
is at 1.2 volts, e.g. logic high. Nevertheless, the NMOS transistor MN
2
cannot be turned “on” sufficiently since the voltage drop across the gate and source of the NMOS transistor MN
2
is no more than 0.4 volts, which barely allows it to overcome the pull-up capability of the PMOS transistor MP
2
. As a result, the output signal is weakly pulled to ground by NMOS transistor MN
2
. Referring to
FIG. 2
, the input signal IN shown is a substantially square wave having a low voltage level of 0 and a high voltage level of 1.2 volts. The output signal OUT has a voltage swing between 0 and 3.3 volts. It can be seen that the output signal OUT is poor and suffers from relatively slow falling time. Such a defect is further exacerbated when the supply voltage V
CCL
for “core” circuits is even lower. Hence, owing to its relative slowness the prior art level shifter
100
cannot be applied to high speed circuitry with “core” circuits having a very low supply voltage.
Accordingly, what is needed is a high speed voltage level shifter that overcomes the disadvantages associated with the prior art.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high speed voltage level shifter for use in circuitry having “core” circuits which operate at a very low supply voltage.
The present invention is directed to a voltage level shifter including a boost circuit and a voltage shifting stage. The voltage level shifter also has an input terminal and an output terminal. The input terminal is used to receive a non-inverted input signal having a first voltage level and a second voltage level, in which the first voltage level is a reference voltage level and the second voltage level is higher than the first voltage level. The boost circuit receives the non-inverted input signal. According to the non-inverted input signal, the boosted circuit produces a boosted signal, where the boosted signal is at a third voltage level when the non-inverted input signal is at the first voltage level, and at the first voltage level when the non-inverted input signal is at the second voltage level. In particular, the third voltage level is higher than the second voltage level. The voltage shifting stage is coupled to the boost circuit. In response to an inverted input signal and the boosted signal, the voltage shifting stage produces an output signal at a fourth voltage level when the inverted input signal and the boosted signal are both at the first voltage level, and at the first voltage level when the inverted input signal is at the second voltage level and the boosted signal is at the third voltage level. Therefore, the output terminal is used to provide the output signal having an output voltage swing between the first voltage level and the fourth voltage level.
In a preferred embodiment, the boost circuit includes a capacitor for producing an intermediate signal at the third voltage level when the inverted input signal is at the second voltage level. The boost circuit also has a first P-type transistor, a second P-type transistor, and a first N-type transistor. In response to the inverted input signal, the first P-type transistor charges the capacitor when the inverted input signal is at the first voltage level. When the non-inverted input signal is at the second voltage level, the first N-type transistor pulls down the boosted signal to the first voltage level. The second P-type transistor passes the intermediate signal to the boosted signal when the non-inverted input signal is at the first voltage level. Further, the capacitor is charged, by way of the first P-type transistor, from a first power source having the second voltage level, such that the intermediate signal substantially remains at the second voltage level when the inverted input signal is at the first voltage level.


REFERENCES:
patent: 5894230 (1999-04-01), Voldman
patent: 5994944 (1999-11-01), Manyoki
patent: 6255888 (2001-07-01), Satomi
patent: 6404237 (2002-06-01), Mathew et al.

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