Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-10-22
2004-07-06
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06759866
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit and a testing method thereof, and especially relates to the semiconductor integrated circuit, operational margins of which can be tested by causing a voltage applied to a step-up power supply line to fluctuate, and the testing method thereof.
2. Description of the Related Art
Battery-driven electronic apparatuses, such as a notebook type PC (Personal Computer) and a cellular telephone terminal, are expanding use of DRAM (Dynamic Random Access Memory). In order to prolong life of a battery used by the apparatuses, the apparatuses are required to operate with minimum power consumption.
Then, in order to reduce the power consumption in DRAM, conventional practices have been to lower the external power supply voltage, and to use the lowered voltage as the operational power supply voltage.
A conventional semiconductor integrated circuit is explained with reference to a semiconductor integrated circuit DRAM
5
shown in FIG.
1
. The semiconductor integrated circuit DRAM
5
shown in
FIG. 1
consists of a memory core
1
, an interface circuit
2
, a logic circuit
3
, and a power supply circuit
4
. The interface circuit
2
receives an address signal and a control signal from an address control line Add-Contl, and a data signal through a data line (DQ) from a CPU (Central Processing Unit) that is not illustrated, provides the above-mentioned signals to the logic circuit
3
, receives signals from the logic circuit
3
, and provides the received signals to the CPU through the data line (DQ). The logic circuit
3
generates a control signal that determines operation timing of each of the internal circuits, based on the address signal, the control signal, and the like received from the CPU, performs writing to and reading from the memory core
1
, and generates writing data and reading data. The power supply circuit
4
supplies predetermined voltages to the memory core
1
, the interface circuit
2
, and the logic circuit
3
, receiving power from an external power supply (a high voltage Vdd and a ground voltage Vss).
Power supplies that the power supply circuit
4
provides are explained with reference to FIG.
2
. The power supply circuit
4
provides a step-down power supply
12
, a step-up power supply
13
, a pre-charge power supply
14
, and a negative power supply
15
to an internal circuit
6
that includes the memory core
1
, the interface circuit
2
, and the logic circuit
3
.
The step-down power supply
12
, the step-up power supply
13
, the pre-charge power supply
14
and the negative voltage power supply
15
generate and provide respectively predetermined voltages, referring to a reference voltage that a reference voltage generator
11
outputs.
The step-down power supply
12
generates a voltage that serves an internal power supply voltage, which is supplied to, e.g., a bit line of the memory core
1
, the interface circuit
2
, and the logic circuit
3
. The step-up power supply
13
generates an elevated voltage, which is supplied to, e.g., a word line of the memory core
1
. The pre-charge power supply
14
supplies a pre-charge voltage, e.g., to the memory core
1
. The negative voltage power supply
15
provides a back bias to a transistor that constitutes a memory cell of the memory core
1
, the memory cell storing an electric charge.
FIG. 3
shows relationships among voltages output from the step-down power supply
12
, the step-up power supply
13
, the pre-charge power supply
14
, and the negative power supply
15
, when the external power supply is turned on, and as the external power supply voltage Vcc increases from zero volts. The voltage output from the negative power supply
15
serves as Vbb
21
(a negative voltage), when the external power supply voltage Vcc reaches a predetermined voltage. The voltage output from the pre-charge power supply
14
serves as Vpr
22
(a pre-charge voltage), when the external power supply voltage Vcc reaches a predetermined voltage. Similarly, the voltages output from the step-down power supply
12
and the step-up power supply
13
are set to Vii
23
(an internal power supply voltage) and Vpp
24
(an elevated voltage), respectively, when the external power supply voltage Vcc reaches a predetermined voltage.
FIG. 4
shows an example of a reference voltage generating circuit of the reference voltage generator
11
. The reference voltage generating circuit includes pMOS
31
, pMOS
32
, nMOS
33
, nMOS
34
, a buffer amplifier
35
, and a resistance element
36
.
The pMOS
31
and pMOS
32
serve as a current mirror circuit. Here, if the power supply voltage Vcc rises, then, current through the pMOS
31
increases, and the nMOS
34
enters a deep conductive state, which increases the voltage drop through the resistance element
36
, and the voltage of a point B rises. Consequently, the nMOS
33
enters a deep conductive state, and the voltage of a point A falls. Conversely, if the power supply voltage Vcc falls, the voltage of the point A rises. Thus, the point A provides a voltage that is stable against a change of the power supply voltage Vcc.
Although the voltage of the point A is compensated against changes of temperature and the external power supply voltage, an influence of a variation in the transistor that constitutes the circuit remains. In order to cope with this, the buffer amplifier
35
is connected to the point A such that the variation in the transistor is removed, and the reference voltage generator
11
outputs the reference voltage (Vref).
FIG. 5
shows an example of a pMOS regulated power supply, which is explained hereunder. The pMOS regulated power supply shown at (A) of
FIG. 5
includes pMOS
41
, pMOS
42
, pMOS
43
, nMOS
44
, nMOS
45
, and nMOS
46
. Here, the pMOS
41
and pMOS
42
serve as a current mirror circuit; the nMOS
44
, nMOS
45
, and nMOS
46
serve as a differential amplifier
48
; and the pMOS
43
functions as a driver
47
. The pMOS regulated power supply receives the external power supply voltage Vcc, which serves as the elevated voltage, and the grounding voltage Vss as the lowest voltage. The pMOS regulated power supply shown at (A) of
FIG. 5
can be represented in a simple way as shown in (B) of FIG.
5
.
Next, operations of the pMOS regulated power supply are described. The differential amplifier
48
compares the output voltage Vii of the driver
47
with the reference voltage Vref, and controls such that the difference between the two voltages, namely, Vref-Vii, becomes zero. Consequently, the output voltage Vii of the driver
47
finally becomes the same voltage as the reference voltage Vref.
The pMOS regulated power supply shown in
FIG. 5
has features such as follows:
(1) the output voltage Vii obtained is independent of load current because of a negative feedback to the output voltage Vii of the driver
47
;
(2) since the external power supply voltage is applied to the source electrode of the driver
47
, sensitivity tends to be high to the noise of the external power supply voltage Vcc; and
(3) in order to enhance the stability of the output voltage Vii against load current change, it is necessary to improve the response of the differential amplifier
48
, which causes the current drain of the differential amplifier
48
to become large in the magnitude of mA.
Advantages of the pMOS regulated power supply include a high flat property of the generated voltage, and a space-saving feature. Disadvantages include high susceptibility to noise, and large power consumption required. Here, the high flat property refers to a property that there is little fluctuation in the output voltage when the load varies and/or little influence when the external power supply voltage is made close to the internal power supply voltage.
FIG. 6
shows an example of an nMOS regulated power supply, which is explained in the following. The nMOS regulated power supply shown at (A) of
FIG. 6
includes a first driver
57
that consists of pMOS
53
, a sec
Fujioka Shin-ya
Mori Katsuhiro
Arent & Fox PLLC
Fujitsu Limited
Karlsen Ernest
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