Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-03-20
2004-07-20
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S185000, C713S322000, C365S227000
Reexamination Certificate
active
06765433
ABSTRACT:
TECHNICAL FIELD
The present invention relates to power management in integrated circuits, and in particular, to the prevention of current leakage in JTAG enabled integrated devices.
BACKGROUND ART
In a TTL compatible chip, each input/output pin on the chip is frequently connected directly to an inverter, which constitute a part of an input buffer. Often, the inverter is formed by having a PMOS transistor and a NMOS transistor joined to one another at their drains. The source of the PMOS device is connected to a power supply, and the source of NMOS device is connected to a ground. In a typical TTL compatible chip that is powered by a 5V power supply source, a legitimate low input signal could range anywhere from −0.5V to 0.8V. Given a low input signal that is near its upper legitimate value of 0.8V, the PMOS transistor in the inverter would be on while the NMOS transistor, which is supposed to be off, would be partially turned on because the voltage at its gate is higher than its threshold voltage. As a result, leakage current would go from the power supply through the PMOS transistor and then through the NMOS transistor to ground. A similar leakage phenomenon is possible for the PMOS transistors as well, albeit the leakage occurs while the input signal is within the legitimate high range from 2V to (Vcc+0.5)V. Given a high input that is near 2V, the NMOS transistor in the inverter would be on while the PMOS transistor, which is supposed to be off, would be partially turned on because the gate to source voltage is more negative than the threshold voltage. As a result, leakage current would go from the power supply through the PMOS transistor and then through the NMOS transistor to ground. Such partial leakage phenomenon is not limited to IC with 5V power supply. Similar problems exist in IC with 3.3V, 2.5V and 1.8V power supply.
A way to prevent such current leakage is to place a second PMOS transistor between the power supply and the first PMOS transistor and a second NMOS transistor between the first NMOS transistor and the ground. The gate of the second PMOS transistor and the gate of the second NMOS transistor would be connected to a low-power signal line that carries an asserted signal only when the chip is in a low-power mode. That way, the power supply would be effectively cut off from the first PMOS transistor and the ground would be effectively cut off from the first NMOS transistor, thereby eliminating the pathway of current leakage.
Although this method works well in preventing current leakage, it is not suitable for chips with boundary scan capability, or chips with ISP (in-system programming) capability. For chips with the boundary scan capability as prescribed by JTAG, the input/output pins must still be ready to receive a signal when the chip is in a power-down mode. For ISP chips, the interface pins also need to be active during power-down mode. The method described above could effectively reduce current leakage while the chip is in power-down mode but the input/output pins would not be responsive to any input signal until the chip is powered up again. Therefore, it would be desirable to have an input/output system that could be turned off during the power-down mode to reduce current leakage but can be reactivated when a signal is detected at its input/output pins.
SUMMARY OF THE INVENTION
The present invention teaches the incorporation of a tristate switching means between each input/output pin and each input buffer with the state of each tristate switching means being controlled by an input transition detection means. The tristate switching means are activated while the chip is in normal high power operation mode, allowing a direct connection between the input/output pins and the input buffers. When the chip goes into power-down mode and a low-power signal is received by the input transition detection means, the tristate switching means are turned off, effectively disconnecting the input/output pins from the input buffers, thereby preventing the leakage of current through partially turned on NMOS or PMOS transistors in the inverters found inside the input buffers. However, when an input signal transition is detected by the input transition detection means, the tristate switching means is turned on again to allow the transmission of the input signal to the input buffer.
REFERENCES:
patent: 6058063 (2000-05-01), Jang
patent: 6266294 (2001-07-01), Yada et al.
patent: 2002/0135398 (2002-09-01), Choi et al.
patent: 2002/0162037 (2002-10-01), Woods et al.
Atmel Corporation
Nguyen Long
Schneck Thomas
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