Method of forming a metal wiring in a semiconductor device

Details Method of forming a metal wiring in a semiconductor device Method of forming a metal wiring in a semiconductor device

2001-06-06

2004-04-20

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S694000, C438S700000, C438S710000, C438S712000

Reexamination Certificate

active

06723645

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
A method of forming a metal wiring in a semiconductor device is disclosed. More particularly, the disclosure relates to a method of forming a metal wiring in a semiconductor device by which copper can be selectively filled and an increase of the via resistance in the copper wiring can be prevented with a diffusion prevention film. Still more specifically, a chemical enhancer layer is formed and a damascene pattern of an ultra-fine structure is then filled with copper using a copper precursor.
2. Description of the Prior Art
As the integration level of semiconductor devices is increased and its signal transfer speed is lowered, there has been an effort to use copper as a metal wiring for transferring current because copper has a substantially lower resistivity than conventional aluminum and, conversely, copper has good electrical conductivity.
However, copper has a disadvantage that the diffusion speed of copper into a silicon oxide used as an insulating film in a semiconductor device is faster than aluminum. Copper atoms that diffuse into the silicon oxide degrades transistors and capacitors in the semiconductor device and thus increase the leakage current. As a result, a diffusion prevention film for preventing diffusion of copper is required. In a dual damascene structure, however, when a copper wiring is formed, as the diffusion prevention film exists in the bottom of the via contact, it functions to increase the via resistance in the copper wiring. Therefore, if a prevention barrier metal having a low resistivity is not suitably selected, it is thought that the effect of resistance will be great and dishing and erosion may be caused by the difference of a selective ratio with the diffusion barrier film during CMP process.
In addition, due to the rapid higher performance and miniaturization of next-generation semiconductor devices, there is a trend toward forming a copper wiring using CVD. However, filling of copper using the CVD method has problems that the deposition speed is slow and the cost is high.
Recently, there is a growing interest in filling of copper wiring using chemically enhanced chemical vapor deposition (CECVD) method. This method, however, has a problem in that the chemical enhancer must be uniformly sprayed and a selective filling method must be applied by which the chemical enhancer is distributed at a specific location, which is difficult to employ.
SUMMARY OF THE DISCLOSURE
A metal wiring in a semiconductor device is disclosed that is capable of preventing an increase in the via resistance by forming a diffusion prevention film on the sidewall of a damascene pattern in the form of a spacer. The method also facilitates select partial filling of the damascene pattern using a copper precursor by selectively forming a chemical enhancer layer within the damascene pattern using a selective reaction property of the chemical enhancer.
The disclosed method of forming a metal wiring in a semiconductor device is characterized in that it comprises: providing a substrate in which an interlayer insulating film consisted of first, second and third insulating films are formed on a lower metal layer; forming a damascene pattern consisting of a trench and a via on the interlayer insulating film; forming a diffusion prevention film spacer on the sidewall of the trench and the via; selectively forming a chemical enhancer layer on the second insulating film constituting the bottom of the trench and on the lower metal layer constituting the bottom of the via; forming a copper layer by means of chemical vapor deposition method; and performing a hydrogen reduction annealing and a chemical mechanical polishing process to form a copper metal wiring.


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Koh et al. “Method of Forming Copper Interconnections and Thin Films Using Chemical Vapor Deposition with Catalyst,” Sep. 6, 2001, USPub. No.: US2001/0019891 A1, 18..*
Communication from Korean Intellectual Property Office Dated Mar. 13, 2003 (2 pages).

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