Universal serial bus receiver having input signal skew compensat

Pulse or digital communications – Receivers

Patent

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Details

375371, 395552, H03K 900

Patent

active

059404485

ABSTRACT:
A receiver includes first and second input nodes and a differential receiver having first and second inputs respectively connected to the first and second input nodes, as well as first and second outputs. First and second delay circuits are respectively connected to the first and second outputs of the differential receiver. First and second single-ended receivers each having an input are respectively connected to the first and second input nodes, the first and second single-ended receivers each having an output. Input glitch prevention circuitry includes third and fourth delay circuits that are respectively connected to the outputs of the first and second single-ended receivers and an OR gate having separate inputs that are respectively connected to the outputs of the first and second single-ended receivers and the outputs of the third and fourth delay circuits. Symmetrical delay compensation circuitry includes a fifth delay circuit that is connected to an output of the OR gate and a first AND gate having separate inputs that are respectively connected to the output of the OR gate and an output of the fifth delay circuit. Second and third AND gates each having an input are connected to an output of the first AND gate and an input is respectively connected to the outputs of the first and second delay circuits. A method of receiving differential input signals is also disclosed.

REFERENCES:
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patent: 5266847 (1993-11-01), Kuo
patent: 5452333 (1995-09-01), Guo et al.
patent: 5467464 (1995-11-01), Oprescu et al.
patent: 5489861 (1996-02-01), Seymour
patent: 5524236 (1996-06-01), Ostrowski
patent: 5587709 (1996-12-01), Jeong
patent: 5608757 (1997-03-01), Smith et al.
patent: 5805639 (1998-09-01), Tonch et al.

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