Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2003-06-04
2004-09-21
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000, C330S257000, C330S261000
Reexamination Certificate
active
06794940
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an operational amplifier circuit, and, more particularly, to a rail-to-rail type operational amplifier circuit, a push-pull type operational amplifier circuit, a current output circuit and an analog switch circuit, which are used as a basic operational circuit in an electronic device.
FIG. 1
is a schematic circuit diagram of a rail-to-rail type operational amplifier circuit
10
according to first prior art.
A first input voltage VIN− is applied to the inverting input terminal (negative input terminal)
11
of the operational amplifier circuit
10
, and a second input voltage VIN+ is applied to the non-inverting input terminal (positive input terminal)
12
thereof. The input terminals
11
and
12
are respectively connected to the gates of P channel MOS transistors (hereinafter referred to as “PMOS transistors”) Q
1
and Q
2
, which constitute a first differential pair
13
. The sources of the transistors Q
1
and Q
2
are connected together and a node between the sources is connected to a high-potential power supply VD via a first current source
14
, which supplies a bias current to the transistors Q
1
and Q
2
. The input terminals
11
and
12
are also respectively connected to the gates of N channel MOS transistors (hereinafter referred to as “NMOS transistors”) Q
3
and Q
4
, which constitute a second differential pair
15
. The sources of the transistors Q
3
and Q
4
are connected together, and a node between the sources is connected to a low-potential power supply GND via a second current source
16
, which supplies a bias current to the transistors Q
3
and Q
4
.
The drains of the transistors Q
1
and Q
2
are connected to the low-potential power supply GND via a pair of NMOS transistors Q
5
and Q
6
, which constitute a first current mirror circuit
17
. The gates of the transistors Q
5
and Q
6
are connected together and a node between the gates is connected to the drain of the transistor Q
5
.
The drain of the transistor Q
6
is connected to the gate of an output NMOS transistor Q
7
. The source of the transistor Q
7
is connected to the low-potential power supply GND and the drain is connected to the high-potential power supply VD via a resistor R
1
. The drain of the transistor Q
7
is connected to an output terminal
18
.
The drains of the transistors Q
3
and Q
4
are respectively connected to second and third current mirror circuits
19
and
20
. The second current mirror circuit
19
includes a pair of PMOS transistors Q
8
and Q
9
. The drain of the transistor Q
3
is connected to the high-potential power supply VD via the transistor Q
8
. The source of the transistor Q
9
is connected to the high-potential power supply VD and the drain of the transistor Q
9
is connected to the drain of the transistor Q
6
.
The third current mirror circuit
20
includes a pair of PMOS transistors Q
10
and Q
11
. The drain of the transistor Q
4
is connected to the gates of the transistors Q
8
and Q
9
via the transistor Q
10
. The source of the transistor Q
11
is connected to the high-potential power supply VD, and the drain of the transistor Q
11
is connected to the drain of the transistor Q
5
.
The first and second current sources
14
and
16
, which are controlled by an unillustrated control circuit, supply bias currents I
1
and I
2
according to the input voltages VIN+ and VIN− as shown in FIG.
2
. Specifically, when the first and second input voltages VIN− and VIN+ are low, the first differential pair
13
drives the transistors Q
5
and Q
6
, and when the input voltages VIN+ and VIN− are high, the second differential pair
15
drives the transistors Q
5
and Q
6
.
As the first and second differential pairs
13
and
15
operate this way, the sum of the bias currents I
1
and I
2
of the first and second current sources
14
and
16
is constant. Even when the potential difference between the input voltages VIN+ and VIN− is zero, therefore, constant currents I
5
and I
6
flow in the transistors Q
5
and Q
6
, respectively.
The currents flowing the transistors Q
1
and Q
2
of the first differential pair
13
are directly supplied to the transistors Q
5
and Q
6
, and the currents flowing the transistors Q
3
and Q
4
of the second differential pair
15
are supplied to the transistors Q
5
and Q
6
via the second and third current mirror circuits
19
and
20
. Accordingly, the current supplies to the transistors Q
5
and Q
6
from the second differential pair
13
are delayed by the operational times of the second and third current mirror circuits
19
and
20
, so that the currents flowing the transistors Q
5
and Q
6
transiently vary.
When the potential difference between the input voltages VIN+ and VIN− is maintained at zero and the absolute value of the input voltage changes, therefore, the currents I
5
and I
6
transiently vary every time the enabling/disabling of the first and second current sources
14
and
16
is switched. This decreases the common mode rejection ratio (CMRR) of the operational amplifier circuit
10
.
When both the first and second current sources
14
and
16
are used and the transistors Q
1
-Q
4
of the first and second differential pairs
13
and
15
are operating, the output transistor control by the first current source
14
and the output transistor control by the second current source
16
are executed simultaneously. In this case, there is a time lag between the output transistor control by the second current source
16
and the output transistor control by the first current source
14
. This reduces the frequency characteristic of the operational amplifier circuit
10
.
Further, the voltages on which the PMOS transistors Q
1
and Q
2
and the NMOS transistors Q
3
and Q
4
operate vary according to the process conditions. Depending on process variation, therefore, the first or second differential pair
13
or
15
may not operate.
Suppose that the operational points of the PMOS transistors Q
1
and Q
2
and the NMOS transistors Q
3
and Q
4
lie between a reference voltage Va and the high-potential power supply VD due to a process variation as shown in FIG.
2
. Then, the NMOS transistors Q
3
and Q
4
do not operate even when the first and second input voltages VIN− and VIN+, which change the first and second bias currents I
1
and I
2
, are supplied.
Therefore, the NMOS transistors Q
3
and Q
4
do not operate even if the first and second input voltages VIN− and VIN+ rise, and the PMOS transistors Q
1
and Q
2
of the first differential pair
13
stop operating when the first and second bias currents I
1
and I
2
are switched from one to the other.
FIG. 3
is a circuit diagram of a push-pull type operational amplifier circuit
300
according to second prior art circuit.
The operational amplifier circuit
300
has a constant current source
11
b
which supplies a constant current Ia to a current mirror circuit
12
b
. The current mirror circuit
12
b
includes NMOS transistors Q
1
b
, Q
2
b
and Q
3
b
. The constant current Ia is supplied to the drain of the transistor Q
1
b
. The drain of the transistor Q
1
b
is connected to the gates of the transistors Q
1
b
, Q
2
b
and Q
3
b
, the sources of which are connected to a low-potential power supply VS. The drain of the transistor Q
2
b
is connected to a current mirror circuit
13
b
, and the drain of the transistor Q
3
b
is connected to a differential input circuit
14
b.
The transistor Q
2
b
has the same size as the transistor Q
1
b
and supplies the current mirror circuit
13
b
with a drain current that is substantially the same as the constant current Ia of the constant current source
11
b
. The transistor Q
3
b
is double the size of the transistor Q
1
b
and supplies the differential input circuit
14
b
with a drain current that is double the constant current Ia of the constant current source
11
b.
The current mirror circuit
13
b
includes PMOS transistors Q
4
b
and Q
5
b
. The drain of the transistor
Arent Fox PLLC.
Nguyen Khanh Van
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