Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...
Reexamination Certificate
2002-04-26
2004-05-11
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Field effect device in non-single crystal, or...
C257S295000, C257S306000, C257S310000
Reexamination Certificate
active
06734459
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor memory cell and a method for fabricating a semiconductor memory cell.
A semiconductor memory cell can be configured as a DRAM (Dynamic Random Access Memory) cell. The semiconductor memory cell may also be configured as a ferroelectric memory cell. These memory cells include a selection transistor and a capacitor. Depending on the construction, the capacitor is a ferroelectric capacitor with a ferroelectric material or a storage capacitor with a dielectric material. The memory cell is referred to as a stacked memory cell if the selection transistor is formed in a substrate, and the storage capacitor is formed over the selection transistor and the substrate. If a ferroelectric material is utilized for capacitor insulation, for instance if PZT (lead zirconate titanate) or SBT (strontium bismuth tantalate) is used, then a temperature step must be performed in an oxygen atmosphere at over 600° C. for longer than a half hour in order to crystallize the ferroelectric material, so that it develops its advantageous ferroelectric characteristics. The disadvantage of exposing the substrate to elevated temperature in an oxygen atmosphere is that conductive regions, for instance silicon or polysilicon regions, are oxidized and thus no longer act as a conductive connection, but rather as an insulator. This can interrupt the electrical connection of the ferroelectric capacitor to the selection transistor.
According to an integration concept of a ferroelectric offset storage cell which is known from the prior art, the lower electrode, which faces the substrate, of the ferroelectric capacitor is fashioned as the common electrode, and the upper electrode of the ferroelectric capacitor forms the respective storage node. This configuration is able to withstand temperature steps at high temperatures in an oxygen atmosphere, because the contact for the electrical connection between the ferroelectric capacitor and the selection transistor is not produced until after the temperature step for recrystallizing the ferroelectric material. As a consequence, an oxidation of this contact owing to the recrystallization is out of the question. The disadvantage of this cell configuration is that the substrate area occupied by this memory cell is larger than 15 F
2
. F represents the minimum lithographically achievable dimension of the underlying semiconductor technology. This is substantially larger than the 8 F
2
which is common today for a DRAM cell. As a consequence, the integration density of this configuration is not particularly large.
According to another configuration of a ferroelectric memory cell taught by the prior art, memory cells of less than 8 F
2
are possible. Because the memory node is situated over the selection transistor, this cell configuration is referred to as a stacked cell. Here, the bottom electrode of the storage capacitor is the storage node, and the top electrode can be constructed as a common counterelectrode of all storage capacitors. Alternatively, the counterelectrode can also be structured individually. In this concept, a conductive terminal is required between the bottom electrode and the selection transistor. Because this terminal is usually formed before the ferroelectric capacitor is formed and must therefore endure the temperature step in an oxygen atmosphere, this electrical terminal is normally protected from oxidation at great expense, including additional costs and processing steps. Furthermore, the ferroelectric capacitor must also be protected from the silicon that diffuses out of the electrical contact. The barrier materials that are known from the prior art are presently not able to withstand a temperature step at an elevated temperature, such as would be required for the recrystallization of a ferroelectric material in order to achieve optimal characteristics. Therefore, lower temperatures and shorter time periods are selected for annealing the ferroelectric layer than would be necessary for an optimal ferroelectric character. Furthermore, when recrystallization temperatures are too low, the tendency of SBT is that large leakage currents flow through it. In addition, greater damage can be caused by hydrogen than would be the case given a well crystallized SBT.
U.S. Pat. No. 5,719,416 describes a semiconductor memory cell with a selection transistor and, provided next to this over the semiconductor substrate, a planar storage capacitor. The storage capacitor includes an elongated lower electrode facing in the direction of the transistor. A doped region of the transistor and the elongated portion of the lower electrode of the capacitor are connected to one another. The connecting contact leads through the insulation layer that separates the transistor and the capacitor, and it touches the elongated portion of the capacitor on this top surface, i.e. the surface which is averted from the substrate.
U.S. Pat. No. 5,604,145 teaches a semiconductor memory cell with a capacitor provided over the selection transistor and the semiconductor substrate. A bottom layer of the capacitor is connected to a doped region of the transistor via a vertical contact.
Published European Patent Application No. EP 0 971 392 discloses a memory cell with a selection transistor and a capacitor with a planar layer sequence alongside thereto.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor memory cell having a transistor and a capacitor that overcomes the above-mentioned disadvantages of the heretofore-known memory cells of this general type. A further object of the invention is to provide a method for fabricating a semiconductor memory cell.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory cell, including:
a substrate having a surface;
a transistor including a doped region disposed in the substrate;
an insulation layer disposed on the substrate and on the transistor;
an electrically conductive contact extending from the doped region through the insulation layer;
a conductive contact layer disposed on the insulation layer, the conductive contact layer having a first surface facing the surface of the substrate, having a second surface averted from the surface of the substrate, and having a lateral surface connecting the first surface of the conductive contact layer to the second surface of the conductive contact layer;
the electrically conductive contact touching the lateral surface of the conductive contact layer;
a capacitor including a bottom capacitor electrode disposed above the insulation layer, a capacitor insulator disposed on the bottom capacitor electrode, and a top capacitor electrode disposed on the capacitor insulator; and
the electrically conductive contact conductively connecting, via the conductive contact layer, the bottom capacitor electrode to the doped region disposed in the substrate.
In other words, with respect to the semiconductor memory cell, the object of the invention is achieved by a semiconductor memory cell including:
a capacitor, a transistor, a substrate with a surface, and an electrically conductive contact, whereby:
the transistor includes a doped region which is disposed in the substrate;
a first insulation layer is disposed on the substrate and on the transistor;
the electrically conductive contact extends from the doped region through the first insulation layer;
a conductive contact layer is disposed on the first insulation layer; and the conductive contact layer includes a surface facing the surface of the substrate, a surface that is averted from the from the surface of the substrate, and a lateral surface which connects these surfaces;
the capacitor includes a lower capacitor electrode, which is provided over the first insulation layer; a capacitor insulator, which is provided on the lower capacitor electrode; and an upper capacitor electrode, which is provided on the capacitor insulator;
the electrically conductive contact conductively connect
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