Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2002-05-13
2004-07-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S459000
Reexamination Certificate
active
06764923
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a method for manufacturing components on a multi-layered silicon wafer by bonding together two initial wafers.
2. Description of the Related Technology
Such a method is known from the publication U.S. Pat. No. 5,583,059. This describes the integration of a so-called “fully depleted” n- and p-FET in combination with an npn heterobipolar transistor (HBT) on a wafer with an insulating intermediate layer (SOI wafer) which has an active layer thickness of less than 0.2 &mgr;m. The silicon layer around the active components is completely removed in order to isolate the individual components and reduce the parasitic capacitances. Furthermore, the thickness of the active layer in the area of the npn transistor is increased by means of an epitaxy process in order to form a collector layer for the manufacture of an npn transistor. Provided that no selective epitaxy process is performed, protective layers, which are removed again in subsequent process steps, are applied in order to protect the FET components. The base of the HBT is also deposited during the multi-stage epitaxy process, during which a so-called drift-HBT is created which does not have a low-doped emitter layer between emitter contact layer and base layer.
The disadvantage of the process architecture described is that the thickness of the active layer has to be substantially increased in the area of the npn transistors in order to adapt electrical parameters such as early voltage and collector series resistance. For this purpose, the collector connector layer (buried layer) must have a thickness which lies in the order of magnitude of the starting thickness of the active silicon layer, whereby it is not possible to increase the doping of the collector connector layer into the range of 10 e17 cm3 with acceptable expenditure, as an activation of this concentration, among other factors, leads to strong out-diffusion.
Another method for manufacturing a component on an SOI wafer is known from the publication S. B. Goody, et al, “High Speed Bipolar on S
2
OI”, in ESSDERC 1998. This describes the manufacture of an npn transistor which has a buried, silicided collector connector layer. For this purpose, a complete silicide layer is formed on the surface of the oxide layer of a first silicon wafer which has a complete oxide layer. An SOI wafer with a complete, buried silicide layer is subsequently manufactured by means of wafer bonding, by bonding the surface of a second silicon wafer to the silicide layer. The second silicon wafer is then thinned to the desired thickness in order to manufacture npn transistors in the remaining silicon layer.
The disadvantage of the process architecture described is that this method cannot be extended to the integration with MOS-transistors with acceptable expenditure, as a complete silicide layer substantially worsens the electrical properties by increasing the parasitic couplings, such as for example the delay time. Furthermore, it is difficult to bond the surface of the complete silicide layer to the surface of another wafer firmly and without offsets.
Furthermore, the process architecture for an npn-HBT for a silicon wafer without an insulating intermediate layer is described in the publication DE 196 09 933, in which the current amplification is increased by creating an epitactic, relatively low-doped emitter layer which suppresses the tunneling of the minorities into the emitter. Furthermore, limiting frequencies above 50 GHz are achieved at relatively low collector currents with a relatively thick, highly-doped collector connector layer (buried layer), which reduces the connection resistance of the collector, and the adaptation of the collector thickness and the doping. Furthermore, a high standard of reproducibility of the electrical parameters is achieved in the manufacturing process by means of a so-called “inside-outside spacer”-technique and avoiding dry etching processes on the emitter windows. The disadvantage of this is that the manufacturing process, which is exclusively oriented to the manufacture of bipolar transistors, can only be integrated with MOS-transistors at great expense. Moreover, further improvement of the HF characteristics is hindered by the use of a conventional silicon wafer as parasitic couplings occur with the substrate.
An objective of the developments in the field of semiconductor technology is to develop methods with which bipolar and HB-transistors for super high frequency applications can be combined with such FE transistors, that have extremely short delay times, without diminishing the electrical properties of any of the types of components involved. On the one hand this requires, for example, very thin active silicon layers with a thickness in the range of 0.2 &mgr;m and less for the MOS-transistors, whereas on the other hand silicon layers thicker than 0.4 &mgr;m are required for the bipolar transistors. Furthermore, the parasitic couplings to the substrate must be suppressed to the greatest possible extent. An important area of application for such combinations of different types of components is the manufacture of highly integrated circuits, which not only have very fast digital signal processing but also make HF outputs available at super high frequencies.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of the type stated at the beginning with which different types of high frequency components can be manufactured together on one wafer with acceptable expenditure.
The above objects have been achieved according to the invention in a method of manufacturing components on a multi-layered silicon wafer, involving bonding together two initial wafers by a wafer bonding process.
According to this, the essence of the invention lies in bonding two wafers to form a new wafer which has buried silicided areas and an insulating intermediate layer, and components of various types, such as for example bipolar transistors as well as FE transistors with in each case optimized HF parameters, are integrated in the uppermost silicon layer on one wafer. For this purpose, a silicon wafer with an insulating intermediate layer is created on a silicon wafer, consisting of a first silicon wafer comprising a surface layer on top of an insulating intermediate layer arranged on a substrate and a second silicon wafer with a surface, by bonding the respective surfaces of the two wafers and, before bonding, at least one silicided area is created within or on the surface of the surface layer of the first silicon wafer, and subsequently at least one insulating layer is applied to the surface of at least one silicon wafer, and after bonding the substrate and at least part of the insulating layer of the first silicon wafer is removed, and then at least one component is manufactured in a series of process steps.
Investigations by the applicant have shown that it is advantageous for the manufacture of high frequency components to select a thin surface layer, preferably with a thickness less than 1.0 &mgr;m. Furthermore, it is advantageous to protect the surrounding regions by means of an oxide mask during the manufacture of the silicide areas, and to create the silicided areas in different depths through further process steps, such as for example silicon etching.
An advantage of the new method in comparison to the previous state-of-the-art is that, before bonding, only those areas on the first wafer are silicided in which the insertion of a silicide layer will improve the electrical properties of the components which are created in a manufacturing process subsequent to the bonding. The silicided areas are buried by bonding the two wafers, whereby the areas lie at different depths within the surface layer. In particular, the buried layers which serve as connecting layers for components can be replaced by means of the buried silicide areas. As the conductivity of silicides is substantially greater than that of doped silicon, the thickness of the uppermost silicon layer and/or the connect
Dietrich Harry
Dudek Volker
Schueppen Andreas
Atmel Germany GmbH
Fasse W. F.
Fasse W. G.
Lattin Christopher
Niebling John F.
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