Memory circuit

Details Memory circuit Memory circuit

2003-04-04

2004-09-21

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185180

Reexamination Certificate

active

06795347

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit and in particular to a memory circuit having at least one non-volatile memory cell and usually a plurality of non-volatile memory cells. In addition, the present invention particularly relates to memory circuits having EEPROM memory cells (EEPROM=electrically erasable and programmable read only memories) and to the set-up of a modified redundant EEPROM memory cell. Additionally, the invention relates to how the logic state (HIGH or LOW) of a memory cell can be read out so that it can be fed to another signal processing.
2. Description of Prior Art
EEPROM memory cells for very large-scale integration applications, as are, for example, to be found in portable computers, are, for example, known from “An enhanced 16K EEPROM”, Lubin Gee, Pearl Cheng, Yogendra Bobra and Rustam Mehta, IEEE J. Sol. Stat. Circ., volume SC-17, no. 5, October 1982, pages 828 to 832 and from “An Experimental 4-Mb Flash EEPROM with Sector Erase”, Mike McConnell and others, IEEE J. Sol. Stat. Circ., volume 26, no.4, April 1991, pages 484-491.
The set-up of memory cells is shown in
FIGS. 1
a
and
1
b.
The memory cell shown in
FIG. 1
a
includes an nMOS transistor
10
comprising a floating gate FG and a control gate CG. The control gate CG is connected to an input
12
of the memory cell. The drain of the nMOS transistor
10
is connected to an output
14
of the memory cell and to the drain of a pMOS transistor
16
serving for impressing a small reading voltage to the drain of the nMOS transistor
10
. The source of the nMOS transistor
10
is connected to a reference potential of, for example, 0 V, i.e. ground. The source of the pMOS transistor
16
is connected to a supply voltage Vsup so that a supply voltage of the EEPROM memory cell shown in
FIG. 1
a
is applied between the source of the pMOS transistor
16
and the source of the nMOS transistor
10
.
The nMOS-EEPROM cell illustrated in
FIG. 1
a
is such a cell as is typically used in VLSI technology (VLSI=very large-scale integration). Thus, above the channel of the nMOS transistor, there is a gate stack of a gate dielectric, a floating gate FG which is insulated from all the other parts of the circuit, another dielectric and the control gate CG. The gate dielectric directly above the channel is mostly formed as thin as possible while that between the floating gate FG and the control gate CG is thicker.
In
FIG. 1
b,
an alternative EEPROM memory cell is shown in which a standard nMOS transistor
18
is used, the gate of which is connected to the input
12
of the memory cell via a capacitor
20
. The gate electrode of the standard nMOS transistor
18
is thus insulated from all the other parts of the circuit by the capacitor
20
so that it represents a floating gate FG.
The fundamental functioning of a conventional EEPROM memory cell, as has been described above referring to
FIGS. 1
a
and
1
b,
will be discussed subsequently. As has been explained, the gate of the nMOS transistor, directly above the channel, is insulated from all the other parts of the circuit, wherein the gate oxide, i.e. the dielectric between the floating gate FG and the channel, is, at least partly, formed thinner than usual. The floating gate is connected to a control gate via either a thicker dielectric (
FIG. 1
a
) or via a capacitor (
FIG. 1
b
), this set-up being electrically equivalent to an nMOS transistor, the gate FG of which is controlled via a capacity.
When the control gate CG is switched to a high voltage, usually between 10 V and 20 V, for a duration of about 10 ms, depending on the thickness of the gate oxide used, there is a voltage division according to the capacitive voltage divider by the capacities between CG and FG as well as between FG and the channel of the nMOS transistor. Since the gate oxide is thinner than the oxide between CG and FG, the capacity between FG and the channel of the nMOS transistor is larger than the capacity between CG and FG so that the bulk of the voltage difference applied between CG and the channel drops at the section CG-FG. The entire voltage must be large enough in order for the field strength in the gate oxide to be sufficient to let charge carriers tunnel from the channel through the gate oxide to the floating gate FG. This process is called Fowler-Nordheim tunneling. Thus a very small current flows. When the high voltage is finally switched off, the charge carriers are trapped at the floating gate FG since it is electrically insulated from its surroundings.
The charge carriers are thus at the floating gate and produce a voltage &Dgr;U at the coupling-in capacitor CG-FG so that the nMOS transistor is controlled by a gate voltage U(CG)-&Dgr;U, U(CG) being the voltage applied across the input
12
to the control gate of the memory cell.
When U(CG) is, for example, selected while reading out the memory cell such that an unprogrammed cell with &Dgr;U=0 V is just operated at the limit between conducting and blocking, the sign of &Dgr;U decides whether the nMOS transistor blocks or conducts. Depending on the definition used, &Dgr;U>0 V is, for example, true for a programmed cell, while &Dgr;U<0 V is true for an erased cell. In order to read out the respective state from the memory cell, a small reading current is impressed via the pMOS transistor
16
into the drain of the nMOS transistor
10
and
18
, respectively. A programmed nMOS transistor blocks so that its drain takes the logic state HIGH corresponding to the voltage Vsup. An erased nMOS transistor conducts so that its drain is pulled to LOW, about 0 V.
For reading out the cells of
FIG. 1
a
or
1
b,
a reading current in the order of magnitude of 1 &mgr;A is fed via the pMOS transistor
16
into the drain of the nMOS transistor
10
and
18
, respectively, while a threshold voltage of the nMOS transistor is applied to the control gate CG. If the nMOS transistor is conductive, it will pull the output
14
to LOW. If the nMOS transistor blocks, the output will be HIGH. This reading process consumes power when the nMOS transistor
10
and
18
, respectively, is conductive.
The capacitor
20
of the memory cell illustrated in
FIG. 1
b
can, for example, be formed by a small poly-poly capacity with a capacitance of about 20 fF.
The reliability of well-known EEPROM memories, as are, for example, described above, can be increased by special coding methods. A simple possibility, for example, is to double-store each bit using two cells and to check in normal operation whether the two variations stored match. When they differ, an error must have occurred. For this method, the control gates of the two bits can be controlled by a common control circuit, which saves area, the two bits must, however, be read out separately and compared to each other, whereby the area consumption for the reading out circuit doubles.
In reality, it often occurs that a programmed “1” can become a “0” but the probability of a “0” becoming a “1” may be significantly lower. Thus, it is better to store a bit as a “1” and a “0”. The bit is recognized as being correct when the two pertaining memory cells are precisely programmed opposite to each other. Such an arrangement, however, requires even more chip area since, in this case, even the control circuit for the control gates of the two memory cells has to be formed separately. Thus also the area demand for storing a bit doubles compared to a simple storage with one cell per bit. Thus the increased reliability is only achieved by a serious chip area consumption.
In case a memory cell loses charge, it is at first not possible to reconstruct the original memory contents. In order to achieve this complicated methods have to be applied, as are developed in the theory for “forward error coding”. In this case, however, in addition to the information to be stored, redundant information from which an error case can be recognized and partly also corrected independently is stored as well. Thus these methods also require additional

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