Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – As active junction in bipolar transistor
Reexamination Certificate
2002-10-11
2004-01-06
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
As active junction in bipolar transistor
C257S517000, C257S557000, C257S565000
Reexamination Certificate
active
06674144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for forming an isolation structure for an integrated circuit, and in particular, to a process for forming an isolation structure for a heterojunction bipolar transistor utilizing a damascene-type process.
2. Description of the Related Art
In order to meet the demand for increased processing speeds, engineers have turned to designs such as high speed heterojunction bipolar transistors (HBT).
FIG. 1
shows a cross-sectional view of such an HBT transistor. Specifically, HBT transistor
100
features Si—Ge alloy base layer
102
overlying single crystal silicon collector
104
. Si—Ge alloy layer
102
includes conductivity-altering dopant of a first conductivity type.
Single crystal silicon collector
104
contains conductivity-altering dopant of a second conductivity type opposite the first conductivity type. Single crystal silicon collector
104
also features heavily doped collector contact
106
and collector sinker
108
of the second conductivity type.
HBT transistor
100
also features polysilicon emitter
110
overlying Si—Ge alloy base
102
. Polysilicon emitter
110
contains an extremely high concentration of dopant of the second conductivity type. Base contact portion
102
a
extends past overlying emitter
110
so as to allow electrical contact to be made with Si—Ge base
102
.
The switching speed of the HBT device can be significantly degraded by effects such as parasitic capacitance. Therefore, substantial isolation between the device and the surrounding environment is required to maintain high speed operation.
Vertical isolation between collector
104
and underlying substrate
112
is provided by buried doped layer
114
containing dopant of the second conductivity type. Lateral isolation between HBT device
100
and adjacent devices formed in substrate
112
is accomplished by deep trench isolation structures
116
. Deep trench isolation structures
116
penetrate to a depth of about 3 &mgr;m into single crystal silicon
112
. Deep trench isolation structures
116
include silicon oxide trench liner layer
118
and borophosphosilicate (BPSG) glass fill material
120
.
While satisfactory for some applications, the conventional HBT architecture shown in
FIG. 1
suffers from a number of disadvantages. One disadvantage is parasitic capacitance. Capacitance arising between extended base contact portion
102
a
and the underlying collector
104
can prolong the switching speed of HBT
100
, adversely affecting its performance in high speed applications.
Therefore, there is a need in the art for an HBT structure exhibiting minimum parasitic capacitance between base and collector.
FIGS. 2A-2F
show a conventional process flow for forming a deep trench isolation structure.
FIG. 2A
shows the starting point for the process, wherein photoresist mask
130
is patterned over single crystal silicon substrate
112
to reveal unmasked regions
132
.
FIG. 2B
shows the etching of single crystal silicon
112
in unmasked regions
132
to form deep trenches
116
.
FIG. 2C
shows removal of the photoresist mask, followed by chemical vapor deposition of silicon dioxide over single crystal silicon
112
, including within deep trenches
116
, to form silicon dioxide trench liner layer
118
.
FIG. 2D
shows removal of silicon dioxide material outside of deep trench
116
, followed by the deposition of BPSG
120
over the entire surface. BPSG
120
penetrates into deep trenches
116
, but the high aspect ratio of the trench interferes with even deposition of BPSG and creates voids
134
.
Accordingly,
FIG. 2E
shows the step of reflowing BPSG
120
by heating. As a result of this reflow the viscosity of BPSG
120
decreases and BPSG
120
settles within deep trench
116
, eliminating the voids.
FIG. 2F
shows removal of BPSG
120
outside of deep trenches
116
. This may be accomplished by chemical-mechanical polishing or another planarization technique such as isotropic etching.
While satisfactory for some applications, the process flow for forming the conventional deep trench isolation suffers from a number of disadvantages. In particular, the conventional process is relatively complex, requiring a number of masking, etching, filling, reflowing, and planarizing steps that increase defect rate and reduce yield.
Therefore, there is a need in the art for a simple and effective process for forming an effective isolation structure for a high-speed bipolar transistor structure.
SUMMARY OF THE INVENTION
The present invention relates to a process for forming an isolation structure for an integrated circuit utilizing a damascene-type technique. In one embodiment of the process flow in accordance with the present invention, a two-tiered silicon dioxide/silicon nitride stack is formed over a single crystal silicon. The top silicon nitride/silicon dioxide tier is etched first in a narrow region. Next, the bottom tier of the silicon nitride/silicon dioxide tier is etched in a broader region to form a trench having a narrow lower portion and a broad upper portion. Epitaxial silicon of the collector is then grown inside the trench, and the base and emitter are created over the epitaxial silicon lying within the trench.
A first embodiment of a process for forming an isolated semiconductor device in an integrated circuit comprises the steps of forming dielectric material over a semiconductor workpiece having a lattice structure, and forming a trench in the dielectric material to stop on the semiconductor workpiece. The trench is filled with a semiconductor material, and a semiconductor device is formed in the semiconductor material.
A first embodiment of an integrated circuit in accordance with the present invention comprises an inter-device isolation structure comprising dielectric material formed over a semiconductor workpiece having a lattice structure, and an active semiconductor device positioned within semiconductor material formed in a trench in the dielectric material and aligned to the lattice structure.
The features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
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T. Yamaguchi et al., “Process Investigations for a 30-GHz &zgr;TSubmicrometer Double Poly-Si Bipolar Technology”, Mar. 1994 IEEE Transactions on Electron Devices, vol. 41, No. 3, pp. 321-329.
K. Washio, “SiGe HBTs and ICs for Optical-Fiber Communication Systems”, 1999 Solid-State Electronics, pp. 1619-1625.
M. Yoshida et al., “A Bipolar-Based 0.5 &mgr;m BiCMOS Technology on Bonded SOI for High-Speed LSIs”, Aug. 1994, IEICE Trans. Electron, vol. E77-C, No. 8, pp. 1395-1403.
National Semiconductor Corporation
Niebling John F.
Pompey Ron
Stallman & Pollock LLP
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