Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-05-13
2004-05-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S173000, C257S209000, C257S665000, C438S132000, C438S467000, C438S600000, C102S202400
Reexamination Certificate
active
06734525
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to microchips and their fabrication. More particularly, the invention relates to fusible structures and fabrication processing related to their integration with microchips.
BACKGROUND OF THE INVENTION
Fuse structures are commonly fabricated as part of microchips. Various objectives are accomplished in the application of such fuses. For example, yield management can be improved through redundant structure designs that provide for the selective disabling of defective portions of a circuit in favor of faultless similar portions. Memory structures are but one well known example of such usage wherein columns, rows or entire arrays of memory elements may be fabricated in complete or partial redundancy and wherein faultless structures are substituted for defective structures by strategically placed and severed fuse structures.
Fuse structures also find utility in allowing for flexibility in circuit design or on-chip programmability wherein microchips may be tailored for particular applications by removal, addition, substitution and the like of distinct structures.
Microchip protection during fabrication handling and processing is yet another example of the utility of such fuse structures. In dynamic random access memory, for example, charge accumulation at sensitive structures may be prevented during fabrication processing by providing preferential charge paths through such fuse structures. The fuse structures are severed when fabrication is substantially complete.
The use of such fuse structures is gaining even more importance as system-on-chip manufacturers integrate ever more chip sub-systems and memory devices together in a single monolithic chip design.
Such microchip fuses are routinely fabricated from metallic or polysilicon materials. Any conductive material may be employed. Generally, a narrowed or neck section of a conductive line is provided as a fusible portion of the line whereby severing or opening of the fusible portion is accomplished by applying a controlled pulse of laser energy. The laser energy superheats the fusible portion and vaporizes the material that forms the fuse and leaves a crater in the surrounding area. Opening a fuse in this manner is, although on a small scale, a very violent procedure. Laser blowing of fuses is known to harbor potential for damaging adjacent circuit structures or substrates including, but not limited to, other fuses which may not be desirably opened. Damage to the microchip, including to laterally and vertically adjacent structures, may be caused by reflected or absorbed laser energy. Structural damage to the microchip substrate is known to occur due to absorbed laser energy and localized stresses. For this reason, adjacent fuses or other circuit structures are spaced outside of the lateral area of influence of the laser and are generally not located below a fuse structure. This of course limits the placement density of fuses and adjacent structures. Lasers having relatively long wavelengths such as infrared lasers may be selected to avoid absorption induced damage since conventional substrate material (e.g. silicon) absorbs shorter wavelengths more readily. However, adoption of longer wavelength lasers also necessitates sparse layouts of fuses and adjacent structures since longer wavelengths have inherently less controllability with respect to spot focus of the laser energy. In other words the area of application over which the longer wavelength laser can be controlled is larger than the area over which a shorter wavelength laser can be controlled.
Various attempts have been made at decreasing the spacing between fuses and adjacent structures including other fuses. U.S. Pat. No. 5,420,455 for example discloses laterally placed barriers characterized by high melting point, non-frangible materials. These barriers, it is taught, are not substantially affected by reflected laser energy and present a physical barrier to the adjacent vaporized material thus limiting expansion of the crater therebeyond. Another type of barrier strategy is disclosed in U.S. Pat. No. 6,297,541 wherein a blocking layer is placed vertically beneath the fuse structure. This blocking layer is also described to be a material that is not substantially affected by applied laser energy. Both of these proposed solutions require additional processing steps, require additional lateral or vertical space, and may do nothing to alleviate localized stresses in the microchip substrate.
FIGS. 1A and 1B
illustrate prior art fuse structure
10
and damage that occurs to surrounding microchip structure from localized stresses. Fuse structure
10
may typically include a lower substrate layer
11
comprising silicon including circuit structure, metalization or other materials, functionality or purposes. Typically located on top of lower substrate layer
11
is a passivation layer
13
such as silicon dioxide or other suitable material of choice. Fuse
15
is a conductor such as metals including alloys or polysilicon and is typically a narrowed or necked portion of a conductor line. Controlled laser energy
17
is applied to the fuse and the laser energy superheats the fusible portion and vaporizes the fuse material and leaves a crater in the surrounding area as can be seen in FIG.
1
B. Localized stresses at the relatively sharp, acute intersections of the sidewalls and bottom of the channel defining the fuse
15
may result in cracking
19
of the surrounding passivation layer
13
.
SUMMARY OF THE INVENTION
Therefore, it is one object of the present invention to provide a microchip fuse structure that when opened by laser energy is resistant to damaging adjacent microchip structures.
It is a further object of the present invention to provide a microchip fuse structure that when opened by laser energy is resistant to damaging adjacent microchip structures without the addition of intervening barriers between the fuse and adjacent structures.
It is a further object of the present invention to provide for the above objects of the present invention by implementing conventional microchip fabrication materials and steps.
These objects and advantages of the present invention are realized by a fuse structure comprising an elongate fusible region at least partially defined by a substrate surface that is characterized by the absence of acute transitions. Preferably, the fuse structure is at least partially defined by a substrate surface that is substantially curvilinear in axial cross-section.
REFERENCES:
patent: 6323111 (2001-11-01), Hui et al.
Chang Yu-Ching
Chou Chieh-Chih
You Jiun-Pyng
Flynn Nathan J.
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
Wilson Scott R
LandOfFree
Low stress integrated circuit fusible link does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low stress integrated circuit fusible link, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low stress integrated circuit fusible link will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3218516