Low stress integrated circuit copper interconnect structures

Details Low stress integrated circuit copper interconnect structures Low stress integrated circuit copper interconnect structures

2003-04-14

2004-07-13

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S751000, C257S762000, C257S771000, C257S758000, C257S748000, C257S050000, C257S052000, C257S543000, C257S529000, C438S652000, C438S653000, C438S672000, C438S688000, C438S669000, C438S671000, C438S687000, C438S612000

Reexamination Certificate

active

06762501

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of integrated circuits and more specifically to a structure and method for reducing the stress in copper interconnect structures.
BACKGROUND OF THE INVENTION
Copper is increasingly being used to form the metal interconnect lines in integrated circuits. Typically, dielectric layers are formed above the semiconductor surface and the copper metal lines are embedded in the dielectric layers using a damascene type process. Currently most of the dielectric layers in which the copper metal lines are formed comprise silicon dioxide. Silicon dioxide is a fairly rigid dielectric material with a dielectric constant of about 3.9.
A major limitation in the operating speed of an integrated circuit is the resistance/capacitance (RC) delays introduced by the resistance of the metal interconnect lines and the capacitance that exists between the various metal lines and the intervening dielectric layers. The use of copper has lead to a reduction in the resistance of the lines compared to some of the previously used materials such as aluminum. The reduction in the capacitance of the copper interconnects is being accomplished by replacing the silicon dioxide dielectric with low k dielectric materials (i.e. materials that have a low dielectric constant). Some of these low dielectric constant materials include organosilicate glass (OSG). In addition to the difference in dielectric constant the low k dielectric materials are ‘softer’ and more flexible that the higher dielectric constant silicon dioxide film.
During integrated circuit formation existing copper lines are often subject to thermal cycles that cause the copper lines to expand. In the case where the rigid high dielectric constant silicon oxide is used, the mechanical strength of the silicon oxide is enough to suppress copper expansion and thus, reduce the tensile stress that is produced in the copper. For the case of the ‘softer’ low k dielectric layers however the copper expands more freely and large tensile stress is produced in the copper lines. This tensile stress has been treated as having mainly hydrostatic components and is most severe in regions of the copper line/dielectric layer structure where asymmetries exist. Such a situation is shown in
FIG. 1. A
dielectric layer
20
is formed over a semiconductor and/or additional layers
10
. A copper metal interconnect
50
is formed in the dielectric layer using standard processing methods. A second dielectric layer
30
is formed over the first dielectric layer
20
and a second copper metal line
60
and a via
70
is formed in the second dielectric layer
30
. The via is a conductive interconnect that connects the copper metal interconnect lines
50
and
60
. A third dielectric layer
40
is formed above the second dielectric layer
30
as shown in the Figure. The asymmetry of the structure is clearly seen in the Figure. During thermal cycling, such as that produced during the formation of the additional layers, the copper lines
60
and
50
will expand and move in a direction given by
80
. The rotational movement of the lines
50
and
60
is caused by the via which ties the lines
50
,
60
together and prevents the lines
50
,
60
from expanding in a straight line. As the lines
50
,
60
move during the thermal cycle voids and/or cracking induced faults
90
are formed in regions of high stress. These voids and/or cracking induced faults
90
can lead to reduced process yield and actual device failure. A method and/or structure is therefore needed to prevent the formation of voids and/or cracking faults in asymmetric copper interconnect lines. The instant invention addresses this need.
SUMMARY OF THE INVENTION
The instant invention results in low stress copper metal interconnect structures in integrated circuits. In particular isolated metal structures are formed adjacent to the ends of terminated metal lines connected by a via. The terminated metal lines represent different levels of metallization and are connected by the via at a position adjacent to the end of each terminated line forming an asymmetric metal structure. The isolated metal structures are formed on the same axis as the adjacent metal lines at distance of less than 0.5 um from the end of each terminated line.


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