Semiconductor memory device including clock generation circuit

Details Semiconductor memory device including clock generation circuit Semiconductor memory device including clock generation circuit

2002-09-05

2004-03-16

Le, Thong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189040

Reexamination Certificate

active

06707758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a clock generation circuit which operates synchronously with the rise and fall of an external clock and which generates an internal clock signal synchronized with the external clock.
2. Description of the Background Art
Generally, an SDRAM (Synchronous Dynamic Random Access Memory) which operates synchronously with an external clock includes therein a clock generation circuit which generates an internal clock signal synchronized with the external clock. The Internal circuits of the SDRAM are controlled using this internal clock.
That is, a circuit which controls data input/output so that the SDRAM exchanges data with the outside of the SDRAM is controlled using this internal clock. Due to this, data input/output timing is greatly influenced by the phase accuracy of the internal clock.
Meanwhile, a DDR SDRAM (Double Data Rate SDRAM) which inputs and outputs data synchronously with the rising edge and the falling edge of an external clock has been developed and put to practical use so as to meet demand for operating a semiconductor device with high frequency. In the DDR SDRAM, the phase difference between the edge of the external clock and the data input/output timing of the DDR SDRAM is particularly required to be smaller than the phase difference in the normal SDRAM. This is because the DDR SDRAM inputs and outputs data at the double frequency rate of the frequency rate of normal SDRAM and the phase difference between the edge of the external clock and the data input/output timing is relatively large to the cycle of the external clock.
FIG. 10
is a timing chart showing data output timing at which data is read from the DDR SDRAM referred to as “DDR-I”. In the DDR SDRAM, a CAS latency CL is set at 2.5 and a burst length BL is set at 4. The CAS latency represents the number of cycles (note that one cycle is from the rise of an external clock EXTCLK to the next rise thereof) since the DDR SDRAM receives a READ command (a command to read data) from the outside until the read data is outputted to the outside of the DDR SDRAM. In addition, the burst length represents the number of bits continuously read in response to the READ command.
Referring to
FIG. 10
, the DDR SDRAM outputs data DQ, which is read data, and a data strobe signal DQS synchronously with external clocks EXTCLK and EXT/CLK. External clock EXT/CLK is a complementary clock signal to external clock EXTCLK. In addition, data strobe signal DQS is a signal which is used as timing at which an external controller receiving data DQ takes in data DQ.
The timing difference tAC between the edge of each of external clocks EXTCLK and EXT/CLK and the output of data DQ is specified to fall within a certain range. In
FIG. 10
, timing difference tAC is controlled to be
0
.
To realize data output shown in
FIG. 10
, a data output circuit needs an operating clock at timing slightly faster than that of the edge of external clock EXTCLK. This is because a delay is generated between the input of an external clock into a semiconductor memory device and the actual output of data from a semiconductor memory device, depending on the capacity of each internal circuit.
That is, external clock EXTCLK is a fixed-cycle signal, and internal clocks CLK_P and CLK_N which are delayed from external clock EXTCLK by an appropriate delay quantity Td and thereby shifted backward by appropriate time Ta from the edge of external clock EXTCLK are generated. It is, therefore, necessary to provide a clock generation circuit capable of controlling delay quantity Td so that data DQ outputted from a data output circuit and data strobe signal DQS outputted from a data strobe signal output circuit, both of which signals operate using internal clocks CLK_P and CLK_N as triggers, satisfy timing difference tAC. The circuit which generates such internal clock signals is referred to as a DLL (Delay Locked Loop) circuit.
The backward amount Ta is determined by propagation time for read data to be taken in using internal clocks CLK_P and CLK_N as triggers and then to be read out to the data output terminal, in a data output circuit. As shown in
FIG. 10
, if the CAS latency is 2.5, the first data of data DQ is outputted synchronously with the rising edge of EXT/CLK (the falling edge of EXTCLK). Therefore, the odd-numbered data of data DQ and the even-numbered data of data DQ are outputted to the outside of the semiconductor memory device using internal clock CLK_N as a trigger and internal clock CLK_P as a trigger, respectively.
FIG. 11
is a schematic block diagram for conceptually explaining the relationship between the above-mentioned DLL circuit and the data output circuit which operates with the internal clocks generated by the DLL circuit and which outputs data DQ to the outside of the semiconductor memory device.
Referring to
FIG. 11
, DLL circuit
100
generates and outputs an internal clock CLK_PF delayed from external clock EXTCLK and an internal clock CLK_NF delayed from external clock EXT/CLK. A repeater
120
receives internal clocks CLK_PF and CLK_NF and outputs DLL clocks CLK_P and CLK_N.
A plurality of data output circuits
500
are provided based on a word organization for DDR SDRAM. In
FIG. 11
, sixteen data output circuits
500
which output data DQ
0
to DQ
15
, respectively, are provided. Each data output circuit
500
inputs DLL clocks CLK_P and CLK_N, is activated by one of DLL clocks CLK_P and CLK_N selected according to an internal signal NZPCNT which is set based on the CAS latency, takes in read data which is read from a memory cell array to a data bus, and outputs the read data to the outside of the semiconductor memory device.
Here, as shown in
FIG. 11
, a signal path from DLL circuit
100
to data output circuits
500
normally has a tree structure. Circuits and signal lines are arranged so as to prevent the data output timings of a plurality of data output circuit
500
from greatly differing among the circuits. Normally, one repeater
120
is arranged for eight or four data output circuits.
FIG. 12
is a functional block diagram for functionally explaining DLL circuit
100
.
Referring to
FIG. 12
, DLL circuit
100
includes variable delay circuits
206
and
208
, pulse generation circuits
210
and
212
, an input/output replica circuit
214
, a phase comparator
216
and a delay control circuit
218
.
An input buffer
202
, which receives external clocks EXTCLK and EXT/CLK inputted into the semiconductor memory device from the outside thereof and which outputs an internal clock BUFFCLK_DLL to DLL circuit
100
, detects the intersection between a potential level when external clock EXTCLK rises and that when external clock EXT/CLK which is the inversion signal of external clock EXTCLK falls, and generates an internal clock BUFFCLK_DLL. On the other hand, an input buffer
204
detects the intersection between a potential level when external clock EXTCLK falls and that when external clock EXT/CLK rises, and generates an internal clock BUFF/CLK_DLL.
Variable delay circuit
206
delays internal clock BUFFCLK_DLL received from input buffer
202
and outputs the delayed clock to pulse generation circuit
210
. Variable delay circuit
206
includes a plurality of delay units which generate delays, connects/disconnects the delay units based on a command from delay control circuit
218
, and thereby delays internal clock BUFFCLK_DLL.
Pulse generation circuit
210
generates internal clock CLK_PF which serves as a pulse signal synchronized with the rising edge of the signal outputted from variable delay circuit
206
.
Variable delay circuit
208
delays internal clock BUFF/CLK_DLL received from input buffer
204
, and outputs the delayed clock to pulse generation circuit
212
. Since the configuration of variable delay circuit
208
is equal to that of variable delay circuit
206
, it will not be repeatedly described herein.
Pulse generation circuit
212
generat

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