PLL for clock recovery with initialization sequence

Details PLL for clock recovery with initialization sequence PLL for clock recovery with initialization sequence

2003-04-11

2004-09-21

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C327S156000, C375S375000

Reexamination Certificate

active

06794945

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuits for reliably sending and receiving non-return-to-zero (NRZ) serial data strings using, for example, phase locked loop (PLL) circuits for deriving clock pulses for sampling the NRZ serial data received.
2. Background Information
Sending a data word serially, that is as a bit stream over a single channel or wire, the receiver must be able to distinguish the beginning of the word and the timing for each individual bit. Framing bits have been devised to indicate the beginning and the end of data words (asynchronous transfers), or means without framing bits to synchronize (synchronized) the sender and receiver to the beginning and end of data words are well known in the art. The problem of determining where the individual bit are in time, as is well known in the field, is more difficult when the bit stream is sent as NRZ. In an NRZ bit stream, if the data word being sent has all one's or zero's, the physical signal is a constant level with no indication of where bit boundaries exist. In such a case there is a need for the receiver system to determine where the individual bits are so that the serial stream can be successfully received.
This sending and receiving of digital data words (or bytes) via a bit stream, in modern system, usually requires converting a parallel data word into a serial form, sending and receiving the serial form, and converting the serial data bits back into a parallel data word. There have been many techniques used to accomplish this task.
One such technique is illustrated in U.S. Pat. No. 4,371,975 ('975) to John M. Dugan. This patent describes an oversampling technique running a clock much faster that the fastest received data rate. Presumably the fastest data rate would occur sending a data word of alternating zero's and one's. In oversampling the resolution of finding the individual bit time locations is a function of the faster clock rate, so the faster the better the ability of finding correct bit locations, but faster clocks will dissipate more power primarily by driving more current through the capacitances involved. And, as the serial data rates and thus the clock rates increase these problems increase.
The linearity of the receiver is also affected by the faster clock rate, where better linearity occurs with faster clock rates, but again at the expense of higher power dissipation.
Another techniques is found in U.S. Pat. No. 6,072,344 ('344) to Larsson. This patent describes comparing phases of input data to a voltage controlled oscillator (VCO). The system locks the VCO to the data rate to provide a clock for receiving the data. This techniques requires a faster clock, but usually not as fast as that described for the over sampling system, but this technique locks slowly, taking tens of microseconds or more.
An objective of the present invention is to provide a system to generate timing signals that accurately determine received bit time positions from a serial data stream without requiring an excessively fast clock while still providing a reasonable locking time.
SUMMARY OF THE INVENTION
The present invention provides a system that generates timing signals that may be used to recover data and framing bits from a serial bit steam while providing a clock with a frequency substantially lower than the bit rate. The inventive system provides a SYNC square wave signal with a period about equal to the word length of the sent data and framing bits. Preferably a phase detector, a charge pump and signal conditioning filters provide a control signal (an up and/or down or error signal) to a voltage controlled oscillation (VCO). An output from the VCO is fed back to the phase detector input for comparing to the SYNC signal, whereupon the system phase locks these two signals. A lock signal is sent to the serial data sending system, whereupon the data sender system may then send framed serial random data signals. In a preferred embodiment, the serial data word sent always begins with a rising edge and ends with a zero.
The VCO provides as many phase shifted outputs as there are random data and framing bits in the word sent. The phase shifted VCO outputs define the bit positions in the serial word sent.
Preferably a reset signal is generated that disables the feedback phase locking loop by holding the control signal so that the VCO phase output signals cannot change. This disabling occurs when random data signals are being received and so prevents the phase locked loop from locking to the data signal. The reset signal enables the phase locking only during the time when the stop bit/start edge occurs.
In a preferred embodiment of the present invention there is no clock generated that has a period shorter than the framed data word being sent. So the fastest clock is typically at least an order of magnitude frequency lower than the random data bit rate.


REFERENCES:
patent: 4371975 (1983-02-01), Dugan
patent: 6072344 (2000-06-01), Larsson
patent: 6628171 (2003-09-01), Chou et al.

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