Pointer processing and path BIP-8 computation for large...

Details Pointer processing and path BIP-8 computation for large... Pointer processing and path BIP-8 computation for large...

2000-09-15

2004-05-18

Jung, Min (Department: 2663)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S535000

Reexamination Certificate

active

06738395

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
1. Microfiche Appendix
Not applicable.
2. Technical Field
The present invention relates to optical communication networks, and in particular to perforating pointer processing and path BIP-8 computation for large concatenated payloads within processing nodes of such a network.
BACKGROUND OF THE INVENTION
Processing network nodes in current optical networks employing CMOS technology have to operate the limited speeds of this technology, which are well below currently available speeds of transmitting data over fiber optic links in such network. In addition, at a network processing node, data may be coming from several different sources, on different connections and at different line clocks. However, at the node, all data must be processed at a local system clock. Accordingly, pointer processor systems are used within processing network nodes to perform timing adjustments on incoming data, in converting the incoming data from a line clock domain to a local system clock domain or ‘shelf-time’ domain.
In order to be able to handle large data frames, pointer processors usually comprise several integrated circuits. In turn, each integrated circuit may comprise a plurality of processing strips, each processing strip having a limited data processing capacity.
A known pointer processor design for SONET (Synchronous Optical Network) or SDH (Synchronous Digital Hierarchy) type data frames is structured on STS (Synchronous Transmission Signal)-n level pointer processing strips, which are capable of processing the equivalent of n STS-1 building blocks from a SONET/SDH frame.
It is often desirable to be able to carry frames comprising large payloads, such as concatenated STS-Nc frames across pointer processing nodes. This implies that for N greater than n, concatenated payloads must be carried across several STS-n level pointer processing strips and possibly even across several chips, when the number of STS-n level pointer processing strips on a single chips is insufficient for the STS-Nc with N very large.
A SONET/SDH STS-Nc concatenated frame is built from N STS-1 building blocks pasted together, but information about the beginning of the SPE is kept only in the pointer bytes, H
1
and H
2
, of the leading STS-1 block in the concatenation. In other words, only the leading STS-1 block in a concatenation comprises valid pointer information within its H
1
and H
2
bytes, whereas the H
1
and H
2
bytes of the trailing STS-1 blocks of the concatenation contain only a concatenation indication. On the other hand, in processing SONET/SDH frame on a pointer processing strip, the strip must have valid pointer information for all the STS-1 blocks within the processed frame. It follows that in processing a concatenated payload across several pointer processing strips, strips processing trailing STS-1 blocks in the concatenation must obtain the valid pointer information from the strip processing the leading STS-1 block in the concatenation.
FIG. 1
illustrates a general scheme of passing pointer information through a pointer processing strip or SYNC block, such that it can operate properly on SONET/SDH type data frames. The pointer processing strip has a pointer interpreter side and a pointer generator side. The pointer interpreter side, working in the line clock domain, receives the incoming data frames on the ‘Data-in’ line, interprets their overhead and writes (W) the payload in an Elastic Store. The pointer generator side, working in the system or shelf clock domain, reads (R) the payload from the Elastic Store and forms new SONET/SDH or other type frames to be passed further to the processing node on the ‘Data-out’ line. The generation of frames by the pointer generator side is based on a SYNC 8K signal, which is an 8 kHz reference indicating the phase of the frame to be formed. The writing and reading of the payload to and from the elastic store, respectively, must be done based on corresponding valid pointer information. In addition, due to the format of the SONET and SDH type frames, valid pointer information on either side of the pointer processor must be available before the reading of the H
3
overhead byte, on the pointer interpreter side, or the generation of the H
3
byte on the pointer generator side. This is due to the fact that the H
3
byte may, in some cases, be part of the actual payload. Let A and B be ports of inputting pointer information to the pointer interpreter and the pointer generator sides, respectively, from a previous pointer processing strip, for example. Also, let A′ and B′ be corresponding ports of outputting pointer information. Considering the pointer processing of a certain frame, let t
1
be a moment in time when the H
3
byte is read from the incoming data and to be a subsequent moment in time when the H
3
byte is added to the generated frame, according to the SYNC 8K signal. According to the above, it follows that for the pointer processing strip to function properly, valid pointer information must be available at A before t
1
and at B before t
2
. Furthermore, if this condition is met and letting &Dgr;t be the propagation delay of pointer information through the pointer processing strip, valid pointer information will be outputted at A′ on or before t
1
+&Dgr;t, and at B′ on or before t
2
+&Dgr;t.
FIG. 2
illustrates a known scheme of passing pointer information along a sequence of pointer processing strips or SYNC blocks #1, #2, #3, etc. Data comes in simultaneously at all blocks on their pointer interpreter sides, through ‘Data-in’ lines. Likewise, data is generated on the ‘Data-out’ lines based on the same SYNC 8K signal running to all three blocks. Assuming that SYNC block #1 receives valid pointer information through A and B at t
1
and t
2
, respectively, then SYNC block #2 receives the valid pointer information from SYNC block #1, at t
1
+&Dgr;t and t
2
+&Dgr;t, respectively, SYNC block #3 receives the valid pointer information at t
1
+2&Dgr;t and t
2
+2&Dgr;t, respectively, and so on. In order for the SYNC blocks to operate properly, the incoming H
3
bytes must be read as follows: on or after t
1
on SYNC block #1, on or after t
1
+&Dgr;t on SYNC block #2, on or after t
1
+2&Dgr;t on SYNC block #3, and so on. Similar conditions apply for the outgoing H
3
bytes in the generated frames. It follows that in this design, only a limited number of pointer processing strips can be used to perform pointer processing on a concatenated payload. Specifically, the number of strips that can be used is roughly equal to T/&Dgr;t, where T is the length of the critical time region during which the pointer information must be propagated. Specifically, this critical time region is defined by time period between the moment when all the necessary pointer information on the strip is available, such as after the H
1
/H
2
bytes of the last STS-3 leader on the strip has been read, and the moment when all the pointer information must be available on the next strip, which is the moment of processing the H
3
byte of the first STS-1 block processed on that strip. In the SONET standard T is approximately 100 nanoseconds(ns). &Dgr;t is dependent on the technology and is currently of the order of several ns, depending on the capacity of the SYNC blocks. For example, one of the technologies currently owned by the assignee of this application, features a 25 ns pointer information propagation delay between STS-48 level processing strips. This implies that a concatenated payload cannot be carried across more than 4 such strips, limiting the size of the concatenation frame to an STS-192c.
In addition to the need for conveying pointer information downward from one SYNC block to the next, along a string of SYNC blocks spanning a concatenated payload, information must also be conveyed in an upward fashion. For example, when the pointer state of an STS-1 block within the concatenation is ‘AIS’ (alarm indication signal), instead of ‘V’, for valid

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