Quadrature signal generation with phase error correction

Details Quadrature signal generation with phase error correction Quadrature signal generation with phase error correction

2002-09-16

2004-07-27

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Phase shift by less than period of input

C327S238000, C327S258000, C331S137000

Reexamination Certificate

active

06768364

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a quadrature signal generator. More specifically, a phase error correction technique is disclosed.
BACKGROUND OF THE INVENTION
To convert radio frequency (RF) signals into baseband signals directly through the mixer of an RF transceiver unit, it is customary to receive a signal from the oscillator, generate a quadrature signal with a phase difference of 90 degrees, and send it to the mixer.
FIG. 1
is a circuit diagram of a polyphase filter used to generate such a quadrature signal. Polyphase filter circuit (
10
) includes resistors (R) and capacitors (C) configured as shown.
In the polyphase filter (
10
) in
FIG. 1
, four resistors (R
1
, R
2
, R
3
, and R
4
) and four capacitors (C
1
, C
2
, C
3
, and C
4
) are connected in series alternately to form a loop. Output terminal (OUT
1
) is set up at the common point of resistor (R
1
) and capacitor (C
1
), output terminal (OUT
2
) is set up at the common point of resistor (R
2
) and capacitor (C
2
), output terminal (OUT
3
) is set up at the common point of resistor (R
3
) and capacitor (C
3
), and output terminal (OUT
4
) is set up at the common point of resistor (R
4
) and capacitor (C
4
). Clock (CLK) of the oscillator (not shown) is input at the common point of capacitor (C
1
) and resistor (R
2
) and at the common point of capacitor (C
4
) and resistor (R
1
), and clock (CLK_b) of the inverse phase with regard to clock (CLK) of the oscillator is input at the common point of capacitor (C
2
) and resistor (R
3
) and at the common point of capacitor (C
3
) and resistor (R
4
).
The polyphase filter (
10
) shown in
FIG. 1
produces four signals with a quadrature phase of 0, 90, 180, and 270 degrees respectively, through output terminals (OUT
1
-OUT
4
) based on the two input signals of clock (CLK) with a phase of 0 degrees and clock (CLK_b) of the inverse phase of 180 degrees generated from the oscillator.
However, if polyphase filter (
10
) of the above configuration is applied to a direct conversion transceiver that uses high frequencies, above 5 GHz, the phase difference between the above output signals (OUT
1
, OUT
2
, OUT
3
, and OUT
4
) would not be exactly 90 degrees. Accordingly, the modulated signals would not be correctly demodulated, and modulation itself would also be difficult. Such phase errors may be caused by bandwidth frequency change, chip process variation during manufacturing of the polyphase filter, impedance mismatch between the resistors and the capacitors of the polyphase filter, and/or a different voltage dependence. It would be useful if such phase errors could be corrected and the undesirable effects of such errors avoided.
BRIEF SUMMARY OF THE INVENTION
A quadrature signal generator is provided including a polyphase filter where four resistive elements and four variable capacitive elements are connected alternately in series to form a loop, including a first output terminal connected to the common point of a first resistive element and a first variable capacitive element a second output terminal connected to the common point of a second resistive element and a second variable capacitive element, a third output terminal connected to the common point of a third resistive element and a third variable capacitive element, a fourth output terminal connected to the common point of a fourth resistive element and a fourth variable capacitive element, a first input terminal at the common point of the first variable capacitive element and the second resistive element and at the common point of the fourth variable capacitive element and the first resistive element, a second input terminal at the common point of the second variable capacitive element and the third resistive element and at the common point of the third variable capacitive element and the fourth resistive element, and wherein the phase corrector is connected between the output terminals and the variable capacitive elements, variably controlling the capacitance of the variable capacitive elements based on the signals output from the output terminals, and a phase corrector that variably controls the capacitance of the variable capacitive elements.


REFERENCES:
patent: 4908532 (1990-03-01), Chadwick
patent: 6035186 (2000-03-01), Moore et al.
patent: 6236847 (2001-05-01), Stikvoort
patent: 6417712 (2002-07-01), Beards et al.
patent: 6560449 (2003-05-01), Liu

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