Method of manufacturing silicon wafer

Details Method of manufacturing silicon wafer Method of manufacturing silicon wafer

2001-09-20

2004-01-20

Rachuba, M. (Department: 3723)

Abrading

Abrading process

Glass or stone abrading

C451S044000, C451S049000

Reexamination Certificate

active

06679759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a silicon wafer. In particular, it relates to a polishing technique for flattening fine roughness existing on a side face of a silicon block or a silicon stack.
2. Description of Related Art
Demand for silicon wafers is increasing year by year in accordance with the spread of solar cells and the like. For example, one solar cell requires about 54 silicon wafers of 5×5 inch square, which are much greater than the number of silicon wafers required in IC and LSI.
The silicon wafer includes polycrystalline and single crystalline silicon wafers, which are manufactured by the following method.
The polycrystalline silicon (polysilicon) wafer is obtained by manufacturing a square polysilicon ingot, cutting the ingot into plural polysilicon blocks
1
with a band saw
20
(
FIG. 4
) and slicing the polysilicon block
1
(FIG.
5
).
FIGS. 4 and 5
show a side face
19
of a silicon block, an edge
21
of a silicon block and silicon wafers
46
.
The single crystalline silicon wafer is obtained by cutting a cylindrical silicon ingot manufactured by a crystal pulling method (generally 1 m in length) into cylindrical single crystalline silicon blocks in a suitable size (generally 40 to 50 cm in length), grinding the single crystalline silicon block to form a flat portion called an orientation flat and slicing the silicon block.
Where the silicon wafer of high dimensional accuracy is required, grinding is carried out in both cases of processing the polycrystalline and single crystalline silicon blocks. Specifically, the grinding is performed by rotating a polishing wheel
45
such as a circular grindstone containing abrasive grains or a diamond wheel at high speed, pressing the silicon block
1
onto the polishing wheel and moving them relatively to each other.
FIG. 6
shows a one-axis stage
7
, a direction
11
along which the stage
7
moves, a motor
5
for rotating the polishing wheel, a two-axes stage
6
and a direction
10
along which the stage
6
moves laterally.
In a conventional process of manufacturing the silicon wafer, a process of improving dimensional accuracy of the silicon block or the silicon stack, or a process of erasing unevenness on the surface of the silicon block or the silicon stack has been carried out. However, flattening of the fine surface roughness existing on its side faces has not been conducted.
The thus obtained silicon wafer is subjected to processing of a side face (may be referred to as a periphery face or a circumferential face).
The periphery processing is carried out by grinding the periphery surfaces of the silicon wafers one by one into a desired configuration in the same manner as a method of processing a glass substrate described in Japanese Unexamined Patent Publication No. Hei 10 (1998)-154321, or by chemical polish (etching).
Since the solar cell requires a large number of silicon wafers as compared with IC and LSI, the above-described periphery processing with respect to each of the silicon wafers consumes a lot of time, investment in equipment and labor. This may delay the supply of the silicon wafers behind the demand. Further, the etching requires equipment for liquid waste treatment, which also involves a problem of equipment costs.
However, without the periphery processing, the silicon wafer may be cracked in a later step for manufacturing the solar cell, which reduces a product yield. Accordingly, there has been demanded development of an efficient method for the periphery processing.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of manufacturing a silicon wafer comprising the step of flattening fine roughness existing on a side face of a silicon block or a silicon stack used for manufacturing the silicon wafer.
According to the present invention, the side face of the silicon block or the silicon stack is flattened to such an extent that dimensional accuracy is improved and surface unevenness is eliminated, i.e., the side face is flattened so that it has surface roughness Ry of 8 &mgr;m or less, preferably 6 &mgr;m or less.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 4084354 (1978-04-01), Grandia et al.
patent: 5405285 (1995-04-01), Hirano et al.
patent: 5484326 (1996-01-01), Hirano et al.
patent: 10-154321 (1998-06-01), None

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