Stacked type semiconductor device

Details Stacked type semiconductor device Stacked type semiconductor device

2002-09-27

2004-09-14

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S686000, C257S698000

Reexamination Certificate

active

06791175

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-375022, filed Sep. 29, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stacked type semiconductor device.
2. Description of the Related Art
In response to an increase in storage capacity required for memory cards and the like, stacked type semiconductor devices (multichip devices) have been proposed which have semiconductor integrated circuit chips (LSI chips) stacked together. The stacked type semiconductor device has a plurality of chips stacked in a vertical direction. Accordingly, this device may be smaller in size (area) than that having chips arranged in a horizontal direction.
In the stacked type semiconductor device, the chips are electrically connected together via, for example, through plugs that penetrate the chips. Thus, to select a desired one of the stacked memory chips of the same structure, the chips must have chip enable bar (/CE) terminals arranged at different positions and which are used to activate (enable) the chip. This prevents the chips from having a common structure, thereby increasing manufacture costs.
To solve this problem, a method has been proposed wherein the chip enable bar terminals for chip selection or terminals to which chip address signals are input are arranged at the same positions of the chips by varying arrangement patterns of bumps used to connect the through plugs in the chips (U.S. Pat. No. 6,239,495). This proposal will be described with reference to FIG.
10
.
Chips C
1
to C
4
are provided with through plugs PG connected together by bumps BP. In the figure, P
1
denotes a terminal part to which chip address signals (CA
0
, CA
1
) used to select (activate) the desired chip are supplied. P
2
denotes a part in which terminals used to specify a chip are formed and in which the bumps BP are arranged in a pattern varying among the chips C
1
to C
4
. That is, in the chip C
1
, all three through plugs PG are connected to a ground potential (Vss). In the chip C
2
, two through plugs PG are connected to the ground potential (Vss). In the chip C
3
, one through plug PG is connected to the ground potential (Vss). In the chip C
4
, no through plugs PG are connected to the ground potential (Vss).
In this manner, the terminals for the chip address signals CA
0
, CA
1
can be arranged at the same positions of the chips by varying the arrangement of the bumps BP and thus the connective relationship among the chips C
1
to C
4
. Then, the desired chip can be selected using the chip address signals (CA
0
, CA
1
), by providing each of the chips C
1
to C
4
with a logic circuit that receives logic values from the terminals (through plugs PG) arranged in the areas denoted by P
1
and P
2
.
However, the above described conventional technique allows the use of chips of the same structure but requires that the arrangement pattern of the bumps is varied among the chips. This hinders a common manufacture process from being appropriately used, thereby increasing manufacture costs. Further, the number of chip specifying terminals arranged in the area denoted by P
2
in
FIG. 10
increases consistently with the number of chips stacked together.
As described above, the conventional stacked type semiconductor device allows an arbitrary chip to be selected by varying the arrangement pattern of the bumps. This hinders a common manufacturing process from being appropriately used, thereby increasing manufacture costs. Further, the number of chip specifying terminals increases with the number of chips stacked together. Accordingly, it is desirable to provide a stacked type semiconductor device that can prevent an increase in manufacture costs or number of terminals.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit holding identification information about the chip, electrically written in the chip, an identification information setting circuit setting the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is coupled to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
According to a second aspect of the present invention, there is provided a stacked type semiconductor device having a plurality of semiconductor integrated circuit chips stacked, each of the semiconductor integrated circuit chips comprising: a holding circuit configured to hold identification information about the chip, to be electrically written in the chip, an identification information setting circuit configured to set the identification information about the chip, in the holding circuit after the plurality of semiconductor integrated circuit chips have been stacked, and at least one setting terminal used to set the identification information about the chip, in the holding circuit, wherein the at least one setting terminal of any semiconductor integrated circuit chip is coupled to the at least one corresponding setting terminal of any other semiconductor integrated circuit chip.
According to a third aspect of the present invention, there is provided a method of manufacturing a stacked type semiconductor device, comprising: preparing a plurality of semiconductor integrated circuit chips, each comprising a holding circuit, electrically writing identification information items about the chips into the holding circuits of the semiconductor integrated circuit chips, stacking the semiconductor integrated circuit chips after writing the identification information items.


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Hosono et al.; “Non-volatile Semiconductor Memory”, U.S. patent application Ser. No. 09/731,910, filed Dec. 8, 2000.
Nakamura et al.; “Semiconductor Memory Device Having a Plurality of Chips and Capability of Outputting a Busy Signal”, U.S. patent application Ser. No. 10/185,645 filed Jun. 28, 2002.
Sasaki; “Multichip Semiconductor Device and Memory Card”, U.S. patent application Ser. No. 09/837,262, filed Apr. 19, 2001.
Oyama et al.; “Laminated-Chip Semiconductor Device”, U.S. patent application Ser. No. 10/156,819 filed May 30, 2002.
Hayasaka et al.; “Multichip Semiconductor Device, Chip Therefor and Method Of Formation Thereof”, U.S. patent application Ser. No. 09/377,486, filed Aug. 20, 1999.

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