Class AB digital to analog converter/line driver

Details Class AB digital to analog converter/line driver Class AB digital to analog converter/line driver

2002-05-31

2004-04-13

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S562000, C330S263000, C330S264000

Reexamination Certificate

active

06720798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to line drivers, and more particularly to high-speed, low-distortion line drivers.
2. Related Art
FIG. 1
shows a conventional output driver cell of a line driver currently employed in (Gigabit) Ethernet products. Each cell includes two differential pairs, enabling tri-state operation. Transistors M
1
a
through M
1
d
are cascodes, implemented using thick-oxide transistors. Transistors M
3
a
and M
3
b
implement the tail current sources of the two differential pairs, each providing a current I
BIAS
. Transistors M
2
a
through M
2
d
are switches (typically thin-oxide transistors) that control to which output terminal the bias current I
BIAS
is sent. More specifically, when V
switch1
and V
switch3
are logical “1”, and V
switch2
and V
switch4
are “0”, the differential output current I
OUT
equals −2I
BIAS
. When V
switch1
and V
switch3
are “0”, and V
switch2
and V
switch4
are “1”, I
OUT
equals 2 I
BIAS
. When V
switch1
through V
switch4
are all “1”, I
OUT
equals zero. (In other words, the digital signal, or data signal, activates the switching transistors M
2
a
-M
2
d
.) A more detailed description of a conventional line driver can be found in commonly assigned U.S. Pat. No. 6,259,745.
V
BIAS
is a DC bias voltage that biases the tail current transistors M
3
a
, M
3
b
to an analog amplifier mode. The switches M
2
a
-M
2
d
send current to either the “+” or the “−” terminal of the output cell, which is a tri-state operating cell. The cell outputs either 2I
BIAS
, 0, or −2I
BIAS
. To output zero current, while operating the cell in class B mode, gates of switches M
2
a
-M
2
d
are switched to ground, and no current appears at the output. Due to the charge injected at node {circle around (1)}, the potential at the gate of M
3
changes, resulting in distortion. Thus, there is unwanted modulation of the DC bias on the gate of the tail current transistors M
3
a
, M
3
b.
As noted above, when I
OUT
has to be zero, V
switch1
through V
switch4
switch to “0”. Unfortunately, switching off all four switches M
2
a
-M
2
d
results in significant distortion of the output signal I
OUT
. The cause of the distortion is explained by
FIG. 2
, which shows half of a line driver output cell. The distortion occurs when all four switches M
2
a
-M
2
d
are switched to “0”. In that case, node {circle around (2)} goes to ground potential. Through the parasitic capacitance C
p
, charge is injected onto node {circle around (1)}. In general, the bias voltage V
BIAS
is generated by a current-biased diode, which has a finite output impedance modeled by R
BIAS
. Furthermore, the parasitic capacitance C
p,bias
associated with the bias voltage V
BIAS
source and transistor M
3
is quite large. As a consequence, the charge injected onto node {circle around (1)} causes the voltage on node {circle around (1)} to drop. It settles back slowly due to the finite voltage source impedance and the large parasitic capacitance connected to node {circle around (1)}. This results in modulation of the tail currents of the differential pairs, and therefore, in modulation of the amplitude of I
OUT
, in other words, unwanted distortion.
I
OUT
(in differential mode)=I
OUT+
−I
OUT−
. I
OUT
is the differential output signal current. Its magnitude depends on the symbol to be transmitted and varies from −40 mA to 40 mA (in 1000BT, 100TX mode), from −100 mA to 100 mA(in 10BT mode). In Class AB mode, I
COMMON
—
MODE
=(I
OUT+
−I
OUT−
)/2 varies from 20 mA to 10 mA, depending on the symbol to be transmitted. Thus:
I
COMMON
—
MODE
=20 mA (in Class-A mode).
I
COMMON
—
MODE
varies from 20 mA to 10 mA (in Class-AB mode), hence the maximum saving of current is 10 mA. When I
COMMON
—
MODE
switches from 20 mA to 10 mA, a glitch is seen that eventually settles to constant value—i.e., producing unwanted distortion.
SUMMARY OF THE INVENTION
The present invention is directed to a line driver that substantially obviates one or more of the problems and disadvantages of the related art.
There is provided a differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding the first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.
In another aspect of the present invention there is provided a differential line driver including first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors and driven by a data signal. A first compound transistor inputs a class AB operation signal at its gate and connected to sources of the first and second switching transistors.
In another aspect of the present invention there is provided a differential line driver includes first and second half-cells, the half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors are connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors and driven by a voltage. A tail current transistor inputs a bias voltage at its gate and connected to sources of the first and second switching transistors, wherein a sum of charge injection at the gate of the tail current transistor is substantially zero during switching.
In another aspect of the present invention there is provided a class AB line driver including first and second half-cells cross connected to positive and negative differential outputs, each half-cell including first and second cascode transistors connected in parallel. First and second switching transistors are connected in series with the first and second cascode transistors. A tail current transistor inputs a bias voltage at its gate and connected to sources of the first and second switching transistors, wherein the bias voltage spikes last less than a clock cycle during switching for Gigabit Ethernet operation.
In another aspect of the present invention there is provided a programmable line driver including a plurality of cells, each cell selectively controlled by class AB operation signal and each cell including first and second half-cells cross connected to outputs of opposite polarity, each half-cell including first and second parallel cascode transistors. First and second switching transistors are each connected in series with the first and second parallel cascode transistors. A compound transistor inputs a bias signal at its gate and connected to sources of the first and second switching transistors, the compound transistor switched to class AB operation by the class AB operation signal, wherein same polarity outputs of the cells are added.
In another aspect of the present invention there is provided a differential line driver including a plurality of cascode transistors connected in parallel and to corresponding polarity outputs of the differential line driver. A plurality of switching transistors are connected in series with corresponding cascode transistors. A plurality of compound transistors input a class AB operation signal at their gates and connected in series with corresponding s

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