Semiconductor device with a low-power operation mode

Details Semiconductor device with a low-power operation mode Semiconductor device with a low-power operation mode

2003-01-03

2004-07-20

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S112000

Reexamination Certificate

active

06765432

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of transition to a low-power operation mode in which the semiconductor device operates on a power lower than a power in a normal operation.
2. Description of the Background Art
As electronic equipment is made smaller and power consumed therein is lowered, a demand for lower power consumption in a semiconductor device mounted to the electronic equipment has increased. Lower power consumption in the semiconductor device can be implemented in the following manner, in accordance with specifications of the electronic equipment to which the semiconductor device is mounted. That is, an operation of a prescribed circuit in the semiconductor device is stopped to reduce current consumption in the circuit to zero, and a frequency rate of a signal input to the prescribed circuit in the semiconductor device is lowered to reduce charging/discharging current in the circuit.
In other words, when the semiconductor device is in the low-power operation mode in which the semiconductor device operates on a power lower than a power in the normal operation, computation or data input/output is not performed in general. Therefore, if the operation is stopped or the frequency rate of the input signal is lowered, for example, in a counting circuit, an arithmetic circuit or the like, power consumed in these circuits is reduced, and a semiconductor device with lower power consumption is implemented.
There are, however, some circuits of which operation cannot be stopped, so long as the semiconductor device is energized.
FIGS. 7 and 8
described below show an example of such circuits.
FIG. 7
is a circuit diagram showing a configuration of an input circuit receiving a low-power operation mode instruction input from the outside.
Referring to
FIG. 7
, an input circuit
260
includes P-channel MOS transistors P
101
to P
104
, N-channel MOS transistors N
101
, N
102
, inverters
101
,
102
, and nodes ND
101
to ND
103
.
P-channel MOS transistor P
101
is connected to an internal power supply node int.Vdd and node ND
101
, and has the gate connected to a ground node GND. P-channel MOS transistor P
102
is connected to internal power supply node int.Vdd and node ND
101
, and receives an output signal of inverter
101
at the gate. P-channel MOS transistor P
103
is connected to nodes ND
101
, ND
102
, and has the gate connected to node ND
102
. P-channel MOS transistor P
104
is connected to nodes ND
101
, ND
103
, and has the gate connected to node ND
102
. N-channel MOS transistor N
101
is connected to node ND
102
and ground node GND, and receives a reference voltage VREF at the gate. N-channel MOS transistor N
102
is connected to node ND
103
and ground node GND, and receives an input voltage SIG at the gate.
Inverter
101
outputs a signal obtained by inverting a logic level of a power control signal PWRCNTL, which will be described later. Inverter
102
has an input node connected to node ND
103
, and outputs as an internal signal intSIG, a signal obtained by inverting the logic level of an input signal.
P-channel MOS transistors P
101
to P
104
and N-channel MOS transistors N
101
, N
102
constitute a current mirror differential amplifier. Input voltage SIG is applied from the outside, depending on whether or not the semiconductor device is subjected to transition to the low-power operation mode. Reference voltage VREF is a threshold voltage of input voltage SIG.
In other words, when input voltage SIG is higher than reference voltage VREF, node ND
103
attains a voltage at which a logic level of a signal is comparable to L level (logic low), and the logic level of internal signal intSIG attains H level (logic high).
Meanwhile, when input voltage SIG is lower than reference voltage VREF, node ND
103
attains a voltage at which the logic level of a signal is comparable to H level, and the logic level of internal signal intSIG attains L level.
The logic level of internal signal intSIG is thus switched, in accordance with variation of the voltage level of input voltage SIG, and switching between the low-power operation mode and the normal operation mode is performed.
A power control signal PWRCNTL is output from a time-counting circuit which will be described later, and attains logic L level in the low-power operation mode. When power control signal PWRCNTL is at L level, P-channel MOS transistor P
102
turns off. Therefore, a direct current in the current mirror differential amplifier is reduced, and power consumed in input circuit
260
is lowered.
In input circuit
260
, however, in the low-power operation mode, power consumed therein can be reduced while the operation thereof cannot be stopped. This is because, when the operation of input circuit
260
is stopped in the low-power operation mode, the semiconductor device can no longer receive input voltage SIG, and cannot return from the low-power operation mode to the normal operation mode.
Next,
FIG. 8
is a circuit diagram showing a configuration of an internal power generating circuit supplying power to an internal circuit in the semiconductor device. In particular, the internal power generating circuit shown in
FIG. 8
internally supplies power to input circuit
260
shown in
FIG. 7
, which receives the low-power operation mode instruction from the outside.
Referring to
FIG. 8
, an internal power generating circuit
300
includes P-channel MOS transistors P
111
to P
113
, N-channel MOS transistors N
111
to N
114
, and nodes ND
111
to ND
114
.
P-channel MOS transistor P
111
is connected to an external power supply node Vdd and node ND
112
, and has the gate connected to node ND
111
. P-channel MOS transistor P
112
is connected to external power supply node Vdd and node ND
111
, and has the gate connected to node ND
111
. N-channel MOS transistor N
111
is connected to nodes ND
112
, ND
113
, and receives reference voltage Vref at the gate. N-channel MOS transistor N
112
is connected to nodes ND
111
, ND
113
, and receives a voltage Vcomp at the gate.
In addition, N-channel MOS transistor N
113
is connected to node ND
113
and ground node GND, and has the gate connected to external power supply node Vdd. N-channel MOS transistor N
114
is connected to node ND
113
and ground node GND, and receives power control signal PWRCNTL at the gate. Further, P-channel MOS transistor P
113
is connected to external power supply node Vdd and node ND
114
, and has the gate connected to node ND
112
. Internal power supply voltage int.Vdd, which is an output of internal power generating circuit
300
, is output to node ND
114
.
P-channel MOS transistors P
111
, P
112
and N-channel MOS transistors N
111
to N
114
constitute the current mirror differential amplifier. Voltage Vcomp is in proportion to internal power supply voltage int.Vdd. Reference voltage Vref corresponds to a target voltage of internal power supply voltage int.Vdd.
When voltage Vcomp in proportion to internal power supply voltage int.Vdd is higher than reference voltage Vref, the voltage level of node ND
112
is raised. Therefore, P-channel MOS transistor P
113
turns off, and internal power supply voltage int.Vdd is lowered. On the other hand, when voltage Vcomp is lower than reference voltage Vref, the voltage level of node ND
112
is lowered. Therefore, P-channel MOS transistor P
113
turns on, and internal power supply voltage int.Vdd is raised. Thus, internal power supply voltage int.Vdd is adjusted to a prescribed voltage based on reference voltage Vref.
In internal power generating circuit
300
, when power control signal PWRCNTL is at L level in the low-power operation mode, N-channel MOS transistor N
114
turns off. Therefore, the direct current in the current mirror differential amplifier is reduced, and power consumed in internal power generating circuit
300
is lowered.
Here, in internal power generating circuit
300
as well, in the low-power operation mode, though power consumed therein can be reduce

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