Shallow trench isolation structure for a bipolar transistor

Details Shallow trench isolation structure for a bipolar transistor Shallow trench isolation structure for a bipolar transistor

2000-10-18

2004-05-18

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including high voltage or high power devices isolated from...

C257S501000, C257S502000, C257S511000, C257S370000, C257S374000

Reexamination Certificate

active

06737721

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device having a shallow trench isolation (STI) structure and, more particularly, to a STI structure for isolation of bipolar transistors in a silicon semiconductor device.
(b) Description of the Related Art
Bipolar transistors have a somewhat complicated structure and fabricated by a more complicated process compared to MOSFETs. The bipolar transistors, however, have several advantages of higher operational speed, higher current driveability and low noise characteristic, and thus are used in a LSI as important constituent elements. For example, a BiCMOS device wherein bipolar transistors and MOSFETs are integrated in a single chip has advantages of both the bipolar transistors and the CMOSFETs, and thus widely used in a variety of applications.
FIG. 1
shows a conventional semiconductor device including bipolar transistors separated by a LOCOS technique, and
FIG. 2
is a sectional view taken along line II—II in FIG.
1
. The semiconductor device
100
is fabricated on a p-type silicon substrate (p-substrate)
102
, and includes a pair of NPN bipolar transistors
104
A and
104
B, which are disposed in a plane symmetry with respect to a plane passing through the center of a p-well
122
.
Each of the pair of bipolar transistors
104
A and
104
B includes an n-welt
107
A or
107
B constituting a collector region, a p-type intrinsic base region
108
A or
108
B disposed on the top portion of the n-well
107
A or
107
B, an n
+
-type emitter region
110
A or
110
B disposed on the intrinsic base region
108
A or
108
B, and a p
+
-type extrinsic base region
112
A or
112
B disposed on the intrinsic base region
108
A or
108
B adjacent to the emitter region
110
A or
110
B.
An n
+
-type collector contact region
114
A or
114
B is disposed in the top portion of the n-well
107
A or
107
B, and is electrically isolated from the extrinsic base region
112
A or
112
B by the LOCOS film
106
. In other words, the intrinsic base region
108
A or
108
B, the emitter region
110
A or
110
B and the extrinsic base region
112
A or
112
B are electrically isolated from the collector contact region
114
A or
114
B by the LOCOS film
106
.
The extrinsic base region
112
A or
112
B, the emitter region
110
A or
110
B and the collector contact region
114
A or
114
B are provided with a base electrode
116
A or
116
B, an emitter electrode
118
A or
118
B and a collector electrode
120
A or
120
B, respectively. The base electrode
116
A or
116
B and the collector electrode
120
A or
120
B are made of silicide layers such as including CoSi
2
and TiSi
2
, whereas the emitter electrode
118
A or
118
B has a two-layer structure including a polysilicon film
118
a
and a silicon oxide film
118
b
. A pair of side walls
118
c
made of silicon oxide film are disposed on respective side surfaces of the two-layer structure.
The p-well
122
is disposed right under the LOCOS film
106
for encircling the n-well
107
A or
107
B and isolating the n-wells
107
A and
107
B from each other by using the isolation function of a p-n junction.
With the development of finer patterning and higher integration of the semiconductor devices, bipolar transistors and MOSFETs are also requested to have finer patterns. This also requires a finer isolation structure, which the LOCOS technique cannot afford due to the presence of a bird's beak in the LOCOS film. A STI structure which is expected to meet the finer patterning is thus noticed in place of using the LOCOS structure.
FIGS. 3A
to
3
F show a fabrication process for the STI structure in a semiconductor device. In
FIG. 3A
, a thin SiO
2
film (not shown) is first formed on a silicon substrate
130
, followed by deposition of a Si
3
N
4
film
132
thereon by a CVD technique. Then, a photoresist film is formed on the Si
3
N
4
film
132
and subjected to patterning to form an etching mask
134
having openings for isolation trenches. The Si
3
N
4
film
132
is then etched using the etching mask
134
to form a Si
3
N
4
hard mask
136
, as shown in FIG.
3
B. The function of the thin SiO
2
film is to prevent damages from occurring on the main surface of the silicon substrate
130
due to the stress by the Si
3
N
4
film
132
. Thereafter, the silicon substrate is subjected to a dry etching using the Si
3
N
4
hard mask
136
to form shallow isolation trenches
138
, as shown in FIG.
3
C.
Subsequently, an insulator film, for example, a SiO
2
film
140
is deposited on the entire surface including the surfaces of the hard mask
136
and the silicon substrate
130
to fill the shallow trenches
138
, as shown in FIG.
3
D. In an alternative, the insulator film may be a TEOS-SiO
2
film deposited by a TEOS-CVD technique.
The SiO
2
film
140
is then subjected to a CMP process until the Si
3
N
4
hard mask
136
is exposed, as shown in FIG.
3
E. In this process, the Si
3
N
4
film has a lower polishing rate compared to the SiO
2
film and thus functions as a stop layer for the polishing.
The Si
3
N
4
hard mask
136
is then removed by etching to obtain the STI structure shown in
FIG. 3F
, wherein device areas are isolated from on another by the shallow isolation trenches
142
.
Consolidated LSIs, wherein an analog signal circuit and a digital signal circuit are integrated in a single chip, are more and more used as the semiconductor devices for use in cellular phones etc. In general, the area for the analog signal circuit has a fewer number of transistor elements compared to the area for the digital signal circuit. Thus, the transistor elements are more sparsely disposed in the analog circuit area compared to the transistor elements in the digital circuit area.
The polishing rate of the CMP process generally depends on the density of the underlying pattern. More specifically, an area of the underlying pattern having a higher-density convex portions of the silicon substrate, which is not the subject area of the CMP process itself, has a lower polishing rate compared to another area of the underlying pattern having a lower-density convex portions of the silicon substrate.
Accordingly, as shown in
FIG. 4A
, in the conventional STI structure fabricated by using the CMP process, the isolation area of the silicon substrate having the lower-density convex portions due to the presence of a wider isolation trench therein may have a dishing portion (or depression) in the isolation area after the CMP process. As a result, after the removal of the Si
3
N
4
film, as shown in
FIG. 4B
, the silicon substrate may have the dishing portion in the isolation area having a wider trench or lower-density concave portions. This causes a problem of an uneven top surface or a step of the silicon substrate, wherein the isolation area is lower than the device area which has higher-density convex portions.
Referring to
FIG. 5A
which shows the detail of the portion of the NPN bipolar transistor
104
A, the step formed by the dishing as described above resides between the wider shallow trench for the isolation area
106
and the device area for the bipolar transistor
104
A. This causes an exposure of a part of the n-well
107
A underlying the p
+
-type extrinsic base region
112
A at the step after the removal of the silicon oxide film on the diffused region for formation of the silicide layer on the silicon substrate, as shown in FIG.
5
A.
After the base electrode
116
A made of a silicide such as CoSi
2
is formed on the extrinsic base region
112
A, the base electrode
116
A may be in short-circuit with the n-well
107
A if the height of the dishing portion is large. This applies to both the bipolar transistors
104
A and
104
B in
FIG. 2
, and degrades the yield rate of the products.
As for the MOSFET, the dishing portion may cause formation of a parasitic transistor at the step portion if the gate electrode extends from the device area along the step toward the dishing portion, as illustrated in FIG.
5
B. This causes degradation of tran

Affiliated with

Also associated with

Rating

Shallow trench isolation structure for a bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Shallow trench isolation structure for a bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Shallow trench isolation structure for a bipolar transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3210587