Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-12-12
2004-05-04
Pert, Evan (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S716000, C324S762010, C324S071500
Reexamination Certificate
active
06731130
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to MOSFETS (metal oxide semiconductor field effect transistors). More particularly, the present invention relates to the field of determining the gate oxide thickness of a MOSFET.
2. Related Art
As the scaling of metal oxide semiconductor field effect transistor (MOSFET) devices approaches deep submicron dimensions (such as channel lengths of 0.10 micrometers currently being developed), the gate oxide thickness scales aggressively into sub-3 nm (nanometers) accordingly. The n-type MOSFET (or NMOSFET) is formed on a p-type substrate. The p-type MOSFET (or PMOSFET) is formed on an n-type substrate. As one of the most critical parameters of the MOSFET, the gate oxide thickness has to be measured accurately to properly use the MOSFET in integrated circuits. Although the MOSFET typically operates in the inversion mode in circuit applications rather than in accumulation mode or depletion mode, the gate oxide thickness is typically measured when the MOSFET is operating in a mode other than the inversion mode.
One conventional technique for determining the gate oxide thickness utilizes ellipsometry and an ellipsometer. According to this technique, a test wafer that has undergone a portion of the fabrication process is provided to the ellipsometer to determine the gate oxide thickness. Unfortunately, this technique is not very accurate when measuring ultra thin gate oxides in the sub-3 nm range. Moreover, this sate oxide thickness measurement does not represent the gate oxide thickness of an actual operational MOSFET that can be used in real circuit applications. Also, this technique is generally destructive with respect to the MOSFET structure.
In addition, a conventional capacitor-voltage (C-V) measurement is utilized to determine the gate oxide thickness, According to this technique, a series of gate voltages are applied to a test MOSFET device and a corresponding capacitance is measured to determine the gate oxide thickness, whereas the test MOSFET device has dimensions (e.g., channel length of 100 micrometers and channel width of 100 micrometers) significantly greater than the dimensions (e.g., channel length of 0.5 micrometers and channel width of 5 micrometers) of an operational MOSFET used in real circuit applications. Unfortunately, this technique is not very reliable for measuring ultra thin gate oxides in the sub-3 nm range for MOSFETS operated in the inversion mode due to large gate direct tunneling currents (which are exponentially dependent on the scaling down of the gate oxide thickness) and the need for a large MOSFET device which cannot sustain formation of the inversion layer during inversion mode operation.
What is needed is a non-destructive system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications. Moreover, what is needed is a system and method for determining the gate oxide thickness when the operational MOSFET is operating in the inversion mode.
SUMMARY OF THE INVENTION
A non-destructive system and method of determining the gate oxide thickness of an operational MOSFET used in real circuit applications is provided. Additionally, the present invention determines the gate oxide thickness when the operational MOSFET is operating in the inversion mode.
According to one method of the present invention of determining the gate oxide thickness of an operational MOSFET, an operational NMOSFET fabricated with a gate oxide formation process is prepared for data measurements. An example of a gate oxide formation process is rapid thermal oxidation which is used to form ultra thin oxides. However, the invention is applicable to MOSFETS fabricated with any other gate oxide formation process. In particular, the drain node and the source node of the operational NMOSFET are coupled to a ground. Then, a range of positive voltages is applied at the gate node of the operational NMOSFET to place the operational NMOSFET in the inversion mode (which is the typical operation node of an operational MOSFET in a real circuit application). For each applied voltage, a gate direct tunneling current is measured at the gate node to generate a plurality of measured data. Continuing, the gate oxide thickness of the operational NMOSFET is determined efficiently by the present embodiment by fitting a gate direct tunneling current model to the measured data and using a gate oxide thickness variable as a fitting parameter.
REFERENCES:
patent: 5798649 (1998-08-01), Smayling et al.
patent: 6188234 (2001-02-01), Abadeer et al.
patent: 6538462 (2003-03-01), Lagowski et al.
Wang Zhigang
Yang Nian
Yang Tien-Chun
Advanced Micro Devices , Inc.
Kobert Russell M.
Pert Evan
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