Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2003-06-05
2004-04-13
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S161000, C341S155000
Reexamination Certificate
active
06720901
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-164829, filed on Jun. 5, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an interpolation circuit having a conversion error correction range for higher-order bits and an A/D conversion circuit utilizing the interpolation circuit, and more particularly to an interpolation circuit that can be realized in a reduced circuit scale, that can be arranged in a multi-stage configuration and that can equalize the common level of the interpolation circuit output, and to an A/D conversion circuit utilizing the interpolation circuit.
2. Description of the Related Art
With the popularization of the digital signal processing technology in recent years, lower power consumption and higher precision have been demanded of A/D conversion circuits that convert analogue signals into digital signals. As an A/D conversion circuit that meets these demands, series-parallel-type A/D conversion circuits utilizing interpolation circuits have been proposed.
FIG. 1
is a circuit diagram illustrating a conventional interpolation-type A/D conversion circuit. This A/D conversion circuit has a reference voltage generation circuit
1
for generating finely divided reference voltages V
0
to V
8
consisting of voltage dividing elements connected in series between reference power sources VRB and VRT, a differential amplifier array
2
for amplifying respectively the differential voltages between the reference voltages V
0
to V
8
and an analogue input voltage VIN, switches
3
, a higher-order comparator array
4
for comparing differential outputs of each of differential amplifiers and for outputting a positive or a negative output and a higher-order encoder
7
for generating a three (3)-bit digital output by encoding an output of the higher-order comparator
4
.
Assuming that the input voltage VIN is positioned between reference voltages V
3
and V
4
, since VIN-V
3
>0 and VIN-V
4
<0, comparators corresponding to the reference voltages respectively outputs a positive output and a negative output so that a higher-order three (3)-bit digital value is detected. That is, where the input voltage VIN is positioned among the reference voltages V
0
to V
8
is detected by the higher-order comparator array
4
and the result is converted into a three (3)-bit digital value by the encoder
7
. A switch in the switches
3
is controlled in response to this higher-order digital value, and the outputs from differential amplifiers connected to the reference voltages V
3
and V
4
respectively are supplied through switches
3
to a pair of differential amplifiers
5
and
6
in the next stage.
From the differential outputs of the differential amplifiers
5
and
6
, a plurality of discrete differential voltages between the differential outputs of the differential amplifiers
5
and
6
are further generated by an interpolation circuit consisting of a voltage dividing element array
8
between the inverted outputs AN and BN of the amplifiers
5
and
6
and a voltage dividing element array
9
between the non-inverted outputs AP and BP of the amplifiers
5
and
6
. The discrete differential voltages V
13
-V
17
, V
23
-V
27
are supplied respectively to the lower-order comparator arrays
10
,
11
and
12
. That is, these interpolated differential voltages are input into the lower-order comparator arrays. Then, a lower-order encoder
13
outputs a lower-order two (2)-bit digital value from the outputs of the comparator arrays
10
,
11
and
12
. A summation circuit
14
sums the higher-order three (3)-bit digital value and the lower-order two (2)-bit digital value and outputs the sum.
FIG. 2
illustrates the principle of the operation of the A/D converter shown in FIG.
1
. The axis of abscissas representing the input voltage VIN shows the relation between the input voltage VIN and the reference voltages V
0
to V
8
. The position of the input voltage VIN for the three higher-order bits is detected according to whether the each output (VIN-V
1
) to (VIN-V
7
) of the differential amplifier array
2
is positive or negative when the amplification factor of the array
2
is assumed to be 1. In this case, since the analogue input voltage VIN is between the reference voltages V
3
and V
4
, the position of the input voltage VIN can be detected from VIN-V
3
>0 (the arrow pointing upward) and VIN-V
4
<0 (the arrow pointing downward) Furthermore, VIN-V
3
and VIN-V
4
are supplied respectively to the lower-order differential amplifiers
5
and
6
and are amplified by a factor of m when the amplification factor of the amplifiers
5
and
6
is assumed to be m.
Then, the discrete differential voltages V
26
-V
16
, V
25
-V
15
and V
24
-V
14
between those amplified differential voltages (VIN-V
3
)×m and (VIN-V
4
)×m are generated by the voltage dividing element arrays
8
and
9
and are supplied to the lower-order comparator array
10
. Since the border between positive outputs and negative outputs of the comparator array
10
is the level of the input voltage VIN at this moment, two (2) lower-order bits can be detected from the outputs of the comparator array
10
.
As apparent from the above description, the interpolation voltages dividing the voltage between the differential outputs of the pair of differential amplifiers
5
and
6
can be generated by the circuit networks of the voltage dividing element arrays
8
and
9
. Therefore, these circuit networks can be deemed to be interpolation circuits. Then, those interpolation voltages are compared in the comparator arrays
10
,
11
and
12
and a lower-order two (2)-bit digital value can be detected using the result of the comparison. A circuit constituted by adding the comparator array to the interpolation circuit can be deemed to be an A/D conversion circuit. These are the definition of the interpolation circuit and the A/D conversion circuit.
If the outputs of the lower-order comparator arrays
10
,
11
and
12
shown in
FIG. 1
are all positive or negative even when the input voltage VIN is between the reference voltages V
3
and V
4
, this means that some conversion error has occurred in detecting the three higher-order bits. Then, in an interpolation-type A/D conversion circuit, extrapolation ranges between the reference voltages V
2
and V
3
, and V
4
and V
5
are provided as conversion ranges for correction in addition to the interpolation range between the reference voltage V
3
and V
4
in the interpolation circuit, so that, when an error has occurred in a higher-order A/D conversion, the error can be corrected by a lower-order A/D conversion circuit.
Such a proposal is described in, for example, Japanese Patent Application Laid-open (Kokai) No. H04-259372 (published on Sep. 29, 1992) and Japanese Patent Application Laid-open (Kokai) No. H04-303537 (published on Nov. 13, 1992). In the A/D conversion circuit proposed in the former application, four (4) differential amplifiers are added in addition to a pair of differential amplifiers. Then, the outputs of those amplifiers are connected to an interpolation circuit consisting of a circuit network and an extrapolation circuit, and an interpolation differential voltage generated by the interpolation circuit and an extrapolation differential voltage generated by the extrapolation circuit are input into a lower-order comparator. Therefore, three higher-order LSB can be corrected. That is, by generating extrapolation differential voltages outside a range between differential voltages (VIN-V
3
)×m and (VIN-V
4
)×m in addition to interpolation differential voltages between the differential voltages (VIN-V
3
)×m and (VIN-V
4
)×m using the two (2) lower-order bits shown in
FIG. 2
, higher-order bits can be corrected. However, this A/D conversion circuit needs to be added with the differential amplifiers
5
Arent & Fox PLLC
Fujitsu Limited
Jean-Pierre Peguy
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