Surface applied passives

Details Surface applied passives Surface applied passives

2002-03-05

2004-03-16

Martin, David (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S763000, C361S734000, C361S766000, C361S720000, C257S762000, C257S765000, C257S677000, C174S050510

Reexamination Certificate

active

06707680

ABSTRACT:

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO A SEQUENCE LISTING A TABLE, OR A COMPUTER PROGRAM LISTING COMPACT DISC APPENDIX
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrical circuit components and to methods of fabrication or production of such components. More particularly, the present invention is directed to passive components (resistors, inductors, terminators and capacitors) built on a surface of a thin flexible polyimide film and attached face down to the surface of a printed wiring board with solder or conductive epoxy in such a way that other components, particularly integrated circuit (IC) packages, can be mounted above them. By “hiding” under the IC packages, the passive components reduce the amount of board surface required for electrical circuitry, without the board manufacturing complexity of a true integral passive process, that is, a process by which passive components are formed within the circuit board itself.
2. Prior Art
As printed circuit boards become increasingly complex, board density increases dramatically. This drives the value of board real estate to higher and higher levels. In conventional surface mount assembly, there is not a great deal of “unused” space. In some of the worst cases, passive components occupy 70% of board surface area, even though the size of individual passive components has decreased.
Because of rapid advances in silicon integration, passive components, even small surface mount varieties, are occupying a larger fraction of printed wiring board real estate, particularly in analog or mixed-signal applications. The need to reduce the space occupied by passives has prompted various development efforts in “integrated passives,” (IP's) which would be buried in thin layers within the PWB itself. But this technology requires fundamental changes in the PWB manufacturing process.
An alternative is a capacitor, resistor, or combination passive network, which combines several passive components into one physical device that is smaller than the area occupied by the individual components. Conventional passive networks are currently built using a variety of techniques, including thin film deposition, on various substrates including ceramics, silicon, and glass. All of these have substantial thickness (>−0.020″) and thus occupy printed wiring board (PWB) area, just as do other surface mount technology (SMT) devices and IC packages themselves. In some cases these passive networks can be combined with packaged or unpackaged ICs to further save PWB area.
U.S. Pat. No. 5,509,599 to Laue, discloses a method for securing a hybrid circuit onto a circuit board. Part of the disclosure describes patterning an array of resistors underneath a packaged, leaded integrated circuit, which is soldered to pads on the hybrid circuit. The resistor array is screen printed onto the hybrid substrate. Other discrete passive components can be attached to the hybrid surface with solder as well. This method requires a sequential assembly process; the IC package and other parts are first soldered to the hybrid substrate. Then the assembled hybrid is soldered to the PWB. The method also requires that the hybrid substrate be larger than the IC package, including the area occupied by IC package leads. Since the hybrid substrate is typically 0.020 inches-0.025 inches thick, the method also increases the height of the final assembly.
U.S. Pat. No. 6,023,407 discloses a structure designed to provide decoupling capacitance to an integrated circuit resting on top of it. While this does remove the decoupling capacitor from occupying additional PWB space, it requires a complicated ceramic construction capable of carrying all signal, power, and ground connections to the IC. It is designed to support an unpackaged, flip chip IC, not an IC in a conventional package. It also requires some form of sequential assembly, since the IC mounts to the passive device, not to the PWB itself.
U.S. Pat. No. 5,386,343 to Pao, discloses a method of placing various electric components underneath upper circuits by placing them in recesses or cavities within the PWB. This invention does not disclose any new types of circuitry. Furthermore, this invention requires additional processing of the PWB, which takes away PWB wiring area and thus decreases the PWB wiring capability.
U.S. Pat. No. 5,034,855 to Komiyana, discloses integrated circuits having capacitors underneath them. However, it does not describe any new type of process for making capacitors or other passive circuits. Furthermore, this invention requires the modification of leads from the integrated circuits by lengthening them so that a conventional capacitor may fit underneath the circuit. Because this requires specially designed integrated circuit packages, this greatly increases the cost of the product.
In contrast with the above-described prior art, the present invention does not require a costly sequential assembly process. The device is smaller in area than the IC package above it. It does not require that the circuits above the passive device have extended leads to provide room for the passive device; it is used with standard packaged ICs. Application of these SAP's (Surface Applied Passives) may be easily integrated into the standard existing process for manufacturing PWB's. It does not require any additional processing of the PWB.
BRIEF SUMMARY OF THE INVENTION
The present invention is directed to passive components; for example resistors, inductors, capacitors, and the like which are built on the surface of a thin flexible polyimide film and attached component side down to a surface of a printed wiring board (PWB) with solder or conductive epoxy in such a way that other components, particularly IC packages such as PLCC's, TSOP's, BGA's, CSP's, and SOIC's can be mounted thereabove. Passive components that once occupied PWB area can be replaced by SAP networks that only occupy the area under the unmodified IC packages.
The placement of the SAP's only involves the addition of the step of adding the SAP's prior to addition of the IC packages. Conventional board assembly equipment can be used to attach the SAP's following the solder application step of the process. SAP's may be soldered to the PWB terminal pads using the same solder paste printing thickness as other SMT components. Thus, incorporation of SAP's into the manufacture of circuit boards is an easy matter. This represents one of the advantages of the invention.
Attaching flexible films populated with passive devices on a PWB in accordance with the present invention leads to cost reduction in electronics manufacturing, miniaturization, lighter products, and better electrical performance. Standard surface mount technology (SMT) passive devices are typically the smallest components available. However, they are reaching their limits in electrical performance and their ability to save board surface area. Also, because of their small size, it becomes increasingly difficult and expensive to mount each device. Additionally, for SMT capacitors, parasitic resistance and inductance associated with the devices degrade electrical performance at higher frequencies. Because of the low profile of the surface applied passives (SAP's) of the present invention, a drastic reduction in board size is achieved by placing the passive flexible films or SAP's under existing leaded or unleaded IC packages. Using polymer films as substrates for these devices also provides other mechanical advantages. Because the polymer film is flexible, it can be mounted just about anywhere on any type of surface. By placing these devices closer to the packages for which they are needed, the full electrical advantages of these passives can be realized. This advantage can be fully appreciated in view of the fact that each IC, in many digital applications, is accompanied by one or more decoupling capacitors connected between

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