Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-07-25
2004-03-16
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S720000
Reexamination Certificate
active
06706631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing, and, more particularly, to a method of controlling sheet resistance of metal silicide regions by controlling the salicide strip time.
2. Description of the Related Art
The manufacture of most devices, such as semiconductor devices, requires a number of discrete processing steps to create the device. With respect to semiconductor devices, a number of discrete steps are needed to produce a packaged semiconductor circuit device from raw semiconductor material. The starting substrate is usually a slice of single crystal silicon referred to as a wafer. Circuits of a particular type are fabricated together in batches of wafers called “lots” or “runs.” The fabrication process creates regular arrays of a circuit on the wafers of a lot. During processing, the individual wafers in a lot may go through individual processing steps one at a time or as a batch. At the completion of wafer processing, the wafers are tested to determine circuit functionality. Later, the wafers are cut to separate the individual integrated circuit devices, the functioning devices are packaged, and further testing is performed prior to use by the customer.
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g. microprocessors memory devices, etc. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. By way of background,
FIG. 1
depicts an illustrative NMOS field effect transistor
10
formed above a surface
14
of a semiconducting substrate
12
between trench isolation regions
25
. The transistor
10
is comprised of a gate dielectric
16
, a gate electrode
18
, a plurality of sidewall spacers
20
and multiple source/drain regions
28
. The transistor
10
is further comprised of metal silicide regions
21
formed on the source/drain regions
28
and on the gate electrode
18
.
The purpose of the metal silicide regions
21
is to reduce the contact resistance of the source/drain regions
28
and the gate electrode
18
. The metal silicide regions
21
are formed by depositing a layer of refractory metal, e.g., cobalt, titanium, etc., above the source/drain regions
28
and the gate electrode
18
. Thereafter, by performing one or more anneal processes, portions of the refractory metal layer in contact with the source/drain regions
28
and the gate electrode
18
are converted to a metal silicide, e.g., cobalt silicide, titanium silicide, etc.
In the process of forming the metal silicide regions
21
above the source/drain regions
28
and above the gate electrode
18
, there comes a point where unreacted portions of the initially-formed layer of refractory metal are removed. For example, in areas where the refractory metal layer is not in contact with polysilicon, e.g., the surface of the sidewall spacers
20
, the refractory metal layer will not be converted to a metal silicide. This removal of the unreacted refractory metal layer is typically accomplished by a dilute acid bath, such as a bath comprised of sulfuric acid and hydrogen peroxide. During this process, portions of the previously formed metal silicide contacts
21
are removed. This, in turn, increases the sheet resistance of the contact, thereby making the operation of the device slower and less efficient, both of which are undesirable.
However, due to the construction of the device, it is imperative that no “bridging” material is left between the metal silicide regions formed above the source/drain regions
28
and the gate electrode
18
. Otherwise, a short circuit path may be established that may severely hamper or prevent the functioning of this device. Thus, in an effort to insure that essentially all of the unreacted refractory metal is removed from places where it should not be, the removal process is designed for a “worst-case” situation. That is, the parameters of the removal process used to remove the unreacted refractory metal are set based upon the greatest thickness anticipated for the refractory metal, i.e., existing methods set the duration of the chemical removal process based upon the thickest layer of refractory metal that may be anticipated by the process. In situations where the layer of refractory metal is less than the maximum thickness anticipated by the design process, this results in subjecting the device to the etching process for a duration longer than would otherwise be required to remove the unreacted portions of the layer of refractory metal. In turn, this over-etching needlessly consumes some of the thickness of the metal silicide regions
21
, which undesirably increases the sheet resistance of the metal silicide regions
21
.
The present invention is directed to a method of forming a semiconductor device that minimizes or reduces some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a method of controlling the sheet resistance of metal silicide regions by controlling the salicide strip time. In one illustrative embodiment, the method comprises forming a layer comprised of a refractory metal, determining a thickness of the layer of refractory metal, and converting a portion of the layer of refractory metal to a metal silicide. The method further comprises determining a duration of an etching process to be used to remove unreacted portions of the refractory metal layer based upon the determined thickness of the refractory metal layer, and performing the etching process for the determined duration.
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patent: 4663191 (1987-05-01), Choi et al.
patent: 5298278 (1994-03-01), Mifune
patent: 5723377 (1998-03-01), Torii
patent: 5844684 (1998-12-01), Maris et al.
patent: 6004878 (1999-12-01), Thomas et al.
patent: 6180469 (2001-01-01), Pramanick et al.
patent: 6218249 (2001-04-01), Maa et al.
patent: 6245622 (2001-06-01), Kawaguchi
Advanced Micro Devices , Inc.
Chen Kin-Chan
Williams Morgan & Amerson
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