Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-09-27
2004-07-06
Le, N. (Department: 2862)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S750010, C324S765010, C438S007000
Reexamination Certificate
active
06759857
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the field of semiconductor wafer manufacturing, and more specifically to methods of preventing partially processed wafers that have to be reworked from contamination front-end operations of the manufacturing line.
(2) Description of the Prior Art
Semiconductor wafer processing typically is a complex process including a large number and variety of processing steps. These processing steps are, during each of the sequences that are executed as part of the step, closely monitored and may result in a complex web of rework, rejects, partial rework, etc. This leads not to the ideal processing sequence where a wafer proceeds from known step to known step but can, result in many diverse flows of partially completed wafers. Wafers may be returned to prior processing steps causing concerns of wafers further down the processing line being contaminated with wafers that have already undergone more advanced steps of processing. It is therefore important to screen for such occurrences and to limit or eliminate the impact of contamination that may be introduced into a wafer processing operation by wafers that are not part of the regular wafer processing flow.
During normal wafer processing, meticulous attention is paid to obtaining and maintaining a clean and particle free environment. This clean environment has a direct impact on wafer yield and therefore on wafer cost. Wafer processing by its very nature tends to introduce impurities into the processing environment, these impurities can for instance be introduced from wafer processing furnaces. Dependent on the type of particle, these particles may diffuse into the semiconductor substrate, especially in areas of the manufacturing process where high frequency operations are being performed on the substrate. This can have a severe detrimental effect on wafer properties making these wafers unsuitable for further use. In other cases, donor or acceptor dopants may be introduced to substrates. These dopants can have a direct affect on the performance of the devices that are at a later stage to be created from these wafers. Yet other impurities can cause surface defects in the surface of the wafer or stacking faults or dislocations in the atomic structure of the substrate. Poor wafer surface can be caused by organic matter that is present in the wafer-processing environment, such as oil or oil related matter.
All of these impurities must be carefully monitored and controlled and must, when present, be removed from the wafer processing environment. This control must be exercised within the cycle of wafer processing steps and at the beginning of the wafer processing process. The frequency and, intensity of such contaminant control operations is highly cost dependent and should, wherever possible, be performed at as low a cost as can be accomplished. These methods of identification and elimination must therefore be simple but yet effective.
To start wafer processing with wafers that are free of contaminants, loose particles are typically first removed from the wafers by means of a wafer scrubbing process. In this way various dusts (atmospheric, silicon and quartz), photoresist chunks and bacteria are removed. Where very small particles are to be removed this is usually accomplished by a polishing operation.
Organic impurities such as hydrocarbons and greases are, after the cleaning process, removed with the use of solvents such as trichloroethylene, acetone, p-xylene, methanol and ethanol. A final cleaning can then be performed using various inorganic chemicals to remove heavy metals, for example. These inorganic chemical mixtures are strong oxidants, which form a thin oxide layer at the wafer surface. This oxide layer is stripped, removing impurities absorbed into the oxide layer.
Also used to further enhance wafer cleaning can be conventional chemical cleaning operations that include acid and rinse baths. These processes remove chemically bonded film from the surface of the wafer.
A further cleaning operation includes the use of mechanical scrubbing operations. These operations tend to be aggressive cleaning operations that use polishing pads affixed to turning tables that hold the substrate that is being polished. Due to the nature of this cleaning operation, the operation needs to be carefully monitored and special precaution needs to be taken to assure that particles that are removed during the operation are removed from the environment.
Typically, the turntable is rotated at various controlled speeds, for, instance 10 to 100 RPM, in a controlled clockwise or counterclockwise direction. A silicon wafer, generally in the form of a flat, circular disk, is held within a carrier assembly with the substrate wafer face to be polished facing downward. The polishing pad is typically fabricated from a polyurethane and/or polyester base material.
Another field in the high density interconnect technology is, the physical and electrical interconnection of many integrated circuit chips to a single substrate commonly referred to as a multi-chip module (MCM). A multi-layer structure is created on the substrate in order to achieve a high wiring and packing density. This multi-layer structure allows for short interconnects and improved circuit performance. Separation of the planes within the substrate, such as metal power and ground planes, is accomplished by separating the layers with a dielectric such as a polyimide. Metal conductor lines can be embedded in other dielectric layers with via openings that provide electrical connections between signal lines or to the metal power and ground planes.
In the indicated processes, great care is used to assure that the surfaces of interfaces have good planarity. In a multilayer structure, a flat surface is extremely important to maintain uniform processing parameters from layer to layer. Layer dependent processing greatly increases processing complexity. Many approaches to producing a planar surface have been incorporated into methods of fabricating high density interconnects and integrated circuit chips in the past. For instance, the lines and vias can be planarized by applying multiple coatings of polyimide which are used to achieve an acceptable degree of planarization. Application of multiple coatings of thick polyimide is however time consuming and creates high stress on the substrate.
The problems associated with prior art polyimide processes have become more troublesome. For example, one of the main difficulties with polyimide processes is that the profiles (i.e. slopes) of the polyimide at the bonding pad edges are not consistent. Rough edges or films having numerous flakes and other defects are pervasive throughout the prior art. In other cases, pieces of photoresist can sometimes become deposited on the surface of the bonding pads causing spikes of unetched passivation layer to be left behind on the bonding pad itself. Although these problems have not prevented the use of conventional polyimide processes in conjunction with standard wire bonding techniques, these shortcomings are unacceptable in the newer, more advanced bonding.
All of the above indicated processing conditions and environments can lead to the introduction of a large number of contaminants and therefore lead to the need for strict control of the environment and the way in which the wafers that are being processed are being routed. Among the contaminants that can accumulate on the surface of a substrate are metals such as copper or aluminum. Control mechanisms that enhance the monitoring of the level of metal deposited on the surface of a wafer prevent unnecessary re-routing and rework of such wafers. Production cost of semiconductor wafers will be reduced if such wafers can be identified so that only wafers that need to be rerouted for rework are entered into the rework cycle.
U.S. Pat. No. 5,820,689 (Tseng et al.) discloses a wet chemical treatment system.
U.S. Pat. No. 5,552,327 (Bachmann et al.) shows a method for monitoring etching using reflectance spectroscopy
Chu Tsui Ping
Kong Sik On
Chartered Semiconductor Manufacturing Ltd.
Kinder Darrell
Le N.
Pike Rosemary L. S.
Saile George O.
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