Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2003-04-22
2004-07-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C363S060000
Reexamination Certificate
active
06762640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bias voltage generating circuit, and particularly to a bias voltage generating circuit for generating a voltage higher than a power supply voltage or lower than the ground voltage and a semiconductor integrated circuit device incorporating therein the bias voltage generating circuit.
2. Description of Related Art
Recently, in order to reduce the power consumption of semiconductor integrated circuit, efforts have been made to lower the voltage level of power supply. As the voltage level of power supply decreases, the absolute value of a threshold voltage of MOS transistor gradually decreases. However, since increase in power consumption during a standby mode needs to be suppressed, an extent to which the threshold voltage of MOS transistor is lowered is forced to become smaller than that to which the voltage level of power supply is lowered. Particularly, in Dynamic Random-Access Memory (DRAM), to maintain a desired hold time for data latch, it is not desirable to reduce the threshold voltage of a transistor within a memory cell unit. However, when the voltage level of power supply is lowered and yet the threshold voltage is maintained at the same level as that used before the voltage level of power supply is lowered, a rate at which DRAM operates cannot be made higher. Accordingly, for example, a technique for supplying a voltage higher than a power supply voltage to a part of DRAM, such as a drive circuit for a word line, in order to make DRAM operate at a higher rate is employed.
FIG. 1
is a circuit diagram illustrating a bias voltage generating circuit disclosed in Japanese Patent Application Laid-open No. 9-106675 (1997). The conventional bias voltage generating circuit includes: an N-channel MOS transistor NT
11
having a drain and a gate connected to a power terminal VCC for supplying a specific positive voltage and a backgate connected to ground; an N-channel MOS transistor NT
12
having a drain and a gate connected to the power terminal VCC and a backgate connected to ground; an N-channel MOS transistor NT
13
having a drain connected to the source of the N-channel MOS transistor NT
11
via the interconnect line
61
, a gate connected to the source of the N-channel MOS transistor NT
12
via the interconnect line
62
, a source connected to a bias voltage output terminal VOUT, and a backgate connected to a ground terminal GND; a capacitive element C
11
having one end connected to the source of the N-channel MOS transistor NT
11
via the interconnect line
61
; and a capacitive element C
12
having one end connected to the source of the N-channel MOS transistor NT
12
via the interconnect line
62
. Note that a capacitive element C
0
is provided to stabilize a bias-voltage output from the bias voltage generating circuit.
The bias voltage generating circuit shown in
FIG. 1
increases or boosts a voltage to a desired voltage level in the following manner. That is, an original clock signal CLK is configured to alternately have high levels and low levels at a specific time interval and the original clock signal is modified to present a clock signal having an amplitude corresponding to a difference between a potential at the power terminal VCC and ground potential, and then, the clock signal is supplied to the other end of the capacitive element C
11
and the other end of the capacitive element C
12
.
FIG. 2
is a timing diagram of how the bias voltage generating circuit operates.
FIG. 2
illustrates how a bias voltage output from the circuit returns to its steady-state voltage when the bias voltage is increased to its steady-state voltage and then, for example, current flows from the bias voltage generating circuit to the outside upon selection of a word line, lowering the bias voltage.
Hereinafter, an electric potential (hereinafter, referred to simply as potential) at the power terminal VCC is simply denoted by VCC and a potential at the ground terminal GND is simply denoted by GND. Furthermore, assume that a threshold voltage is defined as Vt when the backgate voltage of N-channel MOS transistor is zero (i. e., a potential difference calculated by subtracting the potential at source from the potential at backgate is zero) and an increase to Vt in the threshold voltage is defined as &Dgr;V when the potential at backgate is lowered to −VCC relative to the potential at source (i. e., a potential difference calculated by subtracting the potential at source from the potential at backgate is −VCC).
Referring to
FIG. 2
, when the original clock signal CLK is at a low level, the potential of the interconnect line
61
is represented by VCC−(Vt+&Dgr;V) and likewise, the potential of the interconnect line
62
is represented by VCC−(Vt+&Dgr;V). In this case, the potential at a bias voltage output terminal VOUT is assumed to be lower than its steady-state voltage.
When the original clock signal CLK changes to a high level, the clock signal supplied to the other end of the capacitive element C
11
rises from GND to VCC after a little time elapses from the moment the signal CLK changes and therefore, the potential of the interconnect line
61
increases up to 2.times.VCC−(Vt+&Dgr;V). Furthermore, since the clock signal supplied to the other end of the capacitive element C
12
rises from GND to VCC, the potential of the interconnect line
62
also increases up to 2.times.VCC−(Vt+&Dgr;V), turning the N-channel MOS transistor NT
13
to an ON-state.
When the N-channel MOS transistor NT
13
becomes turned on, since an electric charge in the interconnect line
61
moves to the bias voltage output terminal VOUT via the N-channel MOS transistor NT
13
, the potential at the bias voltage output terminal VOUT increases up to the potential of the interconnect line
61
less the threshold voltage (Vt+&Dgr;V) of the N-channel MOS transistor NT
13
, i. e., 2.times.VCC−2.times.(Vt+&Dgr;V), and the potential of the interconnect line
61
decreases down to 2.times.VCC2.times.(Vt+&Dgr;V).
When the original clock signal CLK changes back to a low level, the clock signal supplied to the other end of the capacitive element C
1
decreases from VCC to GND after a little time elapses from the moment the signal CLK changes and therefore, the potential of the interconnect line
62
decreases down to VCC−(Vt+&Dgr;V). Furthermore, although the clock signal supplied to the other end of the capacitive element C
12
decreases from VCC to GND and accordingly, the potential of the interconnect line
62
once decreases down to VCC−2.times.(Vt+&Dgr;V), the potential of the interconnect line
62
is charged by the N-channel MOS transistor NT
12
and then returns to VCC−(Vt+&Dgr;V).
When current does not flow from the bias voltage generating circuit to the outside, the potential at the bias voltage output terminal VOUT keeps its steady-state potential, i. e., 2.times.VCC−2.times.(Vt+&Dgr;V). When current flows from the bias voltage generating circuit to the outside and then the potential at the bias voltage output terminal VOUT becomes lower than its steady-state potential, the potential at the bias voltage output terminal VOUT again returns to 2.times.VCC−2.times.(Vt+&Dgr;V) at the moment the subsequent original clock signal CLK changes to a high level, as is explained in the aforementioned description.
As described above, the conventional bias voltage generating circuit shown in
FIG. 1
is able to generate a bias voltage of 2.times.VCC−2.times.(Vt+&Dgr;V) in its steady-state condition. However, a power supply voltage has increasingly been lowered and in contrast, a threshold voltage inevitably has been gently lowered, as is already described. Accordingly, a difference between a bias voltage generated by the conventional bias voltage generating circuit and a power supply voltage is becoming smaller, eliminating beneficial effects produced by increase in bias voltage. This causes a stron
Callahan Timothy P.
Englund Terry L.
McGinn & Gibb PLLC
NEC Electronics Corporation
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