Clock presence detector comparing differential clock to...

Details Clock presence detector comparing differential clock to... Clock presence detector comparing differential clock to...

2003-07-08

2004-09-14

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S053000, C327S063000

Reexamination Certificate

active

06791369

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to clock detection, and more particularly for methods to detecting clock pulsing by the averaged peak voltage difference, or envelope, of a differential clock.
A technique for increasing the signaling speed of integrated circuits (IC's) is to use differential rather than single-ended signals. A differential pair of signals has two physical lines that move in opposite directions when changing state: one differential signal line is driven to a higher voltage while the other differential line is driven to a lower voltage. At steady-state, one of the differential signal lines is in a high state while the other differential line is in a low state. The difference in voltage between the high and low states can be only a few hundred milli-volts, minimizing voltage swing, capacitive charging delays, and overall signal propagation delay.
Many modern electronic systems are portable, running on limited battery power. Other systems must limit power consumption to reduce cooling requirements or electric power costs. Often some parts of a system are not in continuous use and can be powered down when idle.
FIG. 1
highlights power-down of differential signaling between two chips. Transmitter chip
14
contains differential transmitter
10
, which drives differential output lines V+, V− to opposite states. Differential receiver
12
in receiver chip
16
senses a small voltage difference between differential input lines V+, V− and outputs a single signal to logic inside receiver chip
16
. This signal can be a clock signal generated by transmitter chip
14
.
Transmitter chip
14
may contain control logic that determines when the functions performed by receiver chip
16
are no longer needed. Transmitter chip
14
activates power-down signal PWR-DN which connects to an enable input of receiver chip
16
. Activating PWR-DN causes receiver chip
16
to enter a low-power state.
Sometimes the connection between chips
14
,
16
can be broken, such as when a cable is unplugged.
FIG. 2
shows a fail-safe circuit that blocks data in a receiver when a differential connection is broken. The differential lines driven by differential driver
10
in transmitter chip
14
are disconnected from receiver
12
, perhaps by a disconnected cable. Pull-up resistors
24
,
26
near receiver chip
16
′ pull the differential inputs high when the cable is disconnected. NAND gate
22
detects when both of the differential inputs are in the high state, which does not occur during normal operation.
NAND gate
22
drives the fail-safe signal FSB low when the H-H condition is detected, causing AND gate
20
to output a low, regardless of the data condition sensed by receiver
12
. Thus downstream logic in chip
16
′ is protected from indeterminate data and metastability by the fail-safe circuit.
Often the number of available pins on an integrated circuit chip is limited. Pin functions can be combined to save pins, such as by using an encoded clock using Manchester Encoding, or by using illegal conditions (states of one or more pins) to signal a seldom-used mode.
FIG. 3
shows a power-down mode encoded by an illegal high-high state of differential lines. Transmitter chip
14
′ generates an internal power-down signal PDN when control logic determines that receiver chip
16
should power down. This PDN signal causes modified differential transmitter
10
′ to ignore its data input and instead drive both differential outputs to a high state. Normally one or the other differential line is driven low, so the high-high condition is abnormal or illegal.
NAND gate
22
in receiver chip
16
″ detects when both differential lines are in the high state, and activates the internal power-down signal PDNB by driving it low. This internal power-down signal then powers down logic in receiver chip
16
″. This may include logic downstream of receiver
12
, so that an indeterminate state of the output from receiver
12
does not propagate.
Rather than signaling the power-down condition using the high-high state, the low-low state can be used. However, logic in receiver chip
16
″ must be modified to detect this low-low condition rather than the high-high condition. A disadvantage of this technique is that transmitter
10
in transmitter chip
14
must be modified to generate the high-high or low-low condition. Both chips
14
,
16
must be modified and designed to operate with one another. A standard differential transmitter cannot be used, since a standard differential transmitter does not generate the illegal H-H or L-L state.
Such a modification of the differential transmitter may not always be possible, such as when the differential transmitter is on a personal computer (PC) driving a clock to a memory module. While the differential receiver on the memory module could be modified as new versions of memory modules are designed, the differential transmitter cannot be modified for pre-installed computers.
FIG. 4A
shows a standard differential transmitter with an enable. Standard transmitter chip
28
includes differential transmitter
30
that drives a pair of differential lines to receiver chip
16
″. NAND gate
22
can detect the high-high condition and activate a power-down mode in receiver chip
16
″. However, differential transmitter
30
cannot drive both differential lines high.
When the enable input to differential transmitter
30
is deactivated, differential transmitter
30
stops driving both differential lines and enters a high-impedance (high-Z) state. This high-Z state is not the same as a high state.
FIG. 4B
is a waveform of a standard differential transmitter entering the high-Z state. When enable ENA is high, differential transmitter
30
drives differential lines V+, V− opposite states as the data input to differential transmitter
30
toggles. When ENA goes low, differential transmitter
30
is disabled and stops driving the differential lines. The differential lines then float.
If the differential lines were completely isolated, the voltage would remain in the prior state. However, capacitive coupling from other signals and leakage can upset the voltages on the differential lines, causing them to drift. Leakage between the two differential lines can cause the voltages to equalize over time. Any terminating resistors can also alter the voltages on the differential lines.
Since NAND gate
22
in receiver chip
16
″ only detects dual high voltages, the floating differential lines do not necessarily trigger the power-down state. Indeed, as other signals capacitivly couple into the differential lines, receiver chip
16
″ can pass in and out of the power-down state, causing logical problems. Thus the high-impedance state is not as useful as the dual-high state for signaling power-down, causing a non-standard differential drive to be needed.
Various circuit to detect the presence or absence of a clock signal are known. While such clock detectors are useful, a clock detector that detects a differential clock is desirable. A differential-clock detector circuit is desirable.


REFERENCES:
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patent: 4672325 (1987-06-01), Murai
patent: 4736117 (1988-04-01), Wieser
patent: 5343164 (1994-08-01), Holmdahl
patent: 5894284 (1999-04-01), Garrity et al.
patent: 5986497 (1999-11-01), Tsugai
patent: 6016566 (2000-01-01), Yoshida
patent: 6281699 (2001-08-01), Bishop
patent: 6333646 (2001-12-01), Tsuzuki
patent: 6549072 (2003-04-01), Vernon
patent: 6573779 (2003-06-01), Sidiropoulos et al.

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