Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Reexamination Certificate
2002-05-10
2004-04-06
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
C341S065000, C710S057000, C348S419100, C382S246000
Reexamination Certificate
active
06717535
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method for preventing an input of variable length codes from being interrupted. In particular, the present invention relates to a system and method for preventing an input of variable length codes of an MPEG (Motion Picture Experts Group) signal from being interrupted.
2. Description of the Related Art
An MPEG signal contains a video variable length code and an audio variable length code. The video variable length code is obtained by compressing a video signal corresponding to motion compensated bi-directional inter-frame prediction encoding system using discrete cosine transforming system. The audio variable length code is obtained by compressing an audio signal corresponding to sub-band encoding system. An MPEG signal is used to highly efficiently transmit audio and video signals. In addition, an MPEG signal is used to record audio and video signals to a record medium such as a DVD (Digital Versatile Disc) or a hard drive.
Since an MPEG signal is a digital signal, even if it is copied, the quality thereof is not deteriorated. Thus, when an MPEG signal is illegally copied, the copyright of the content producer is infringed.
To solve such a problem, a technology for inserting an electronic watermark that represents a copyright into DCT (Discrete Cosine Transform) coefficient codes of an MPEG signal that is recorded on a record medium such as a DVD has been developed. In addition, a technology for inserting an electronic watermark for controlling a copying operation into DCT coefficient codes of an MPEG signal that is recorded on a record medium such as a DVD has been developed. In particular, as one type of an electronic watermark for controlling a copying operation, an electronic watermark that does not vary the code amount has been developed. Such an electronic watermark has been used by a content producer. A circuit that detects such an electronic watermark is disposed in a DVD player or a DVD recorder. In the case that such an electronic watermark represents that a copying operation is prohibited, when an MPEG signal into which such an electronic watermark has been inserted is tried to be copied from one DVD to another DVD, the MPEG signal cannot be copied. Thus, the copyright of the content producer can be protected.
When an MPEG signal is copied from one DVD to another DVD, it is preferred to perform it at high speed without need to output a sound and a picture to a speaker and a monitor from a view point of high efficiency. Thus, when an MPEG signal is copied from one DVD to another DVD, a DVD reproducing drive (not DVD player) that reproduces an MPEG signal at a speed several times (or more times) higher than the regular reproducing speed and a DVD recording drive (not DVD player) that records an MPEG signal at a speed several times (or more times) higher than the regular recording speed.
However, to prevent an MPEG signal from being illegally copied, although the DVD drive does not need to provide an MPEG decoding device, the DVD drive should be equipped with a function for decoding a reproduced MPEG signal to DCT coefficients and detecting an electronic watermark from the obtained DCT coefficients.
As an example of related art,
FIG. 1
is a block diagram showing a circuit that decodes an MPEG signal to DCT coefficients and detects an electronic watermark from the obtained DCT coefficients.
Referring to
FIG. 1
, the circuit has an input interface
901
, a buffer
902
, a video elementary stream extracting circuit
903
, a barrel shifter
904
, a variable length decoding device
905
, a controlling portion
906
, an inverse quantizing device
907
, and an electronic watermark detecting device
908
.
The input interface
901
and an input side of the buffer
902
is driven by an external interface clock that also drives an output interface of a pre-stage portion (not shown). An output side of the buffer
902
and circuits downstream thereof are driven by an internal clock that does not synchronize with the external interface clock.
In addition to an MPEG signal reproducing device such as a DVD reproducing drive, the electronic watermark detecting circuit may be built in an MPEG signal recording device such as a DVD recording drive or an interface device disposed between an MPEG signal reproducing device and an MPEG signal recording device. When an electronic watermark detecting circuit is built in an MPEG signal reproducing device, the pre-stage portion contains a mechanism of an MPEG signal reproducing device, a reproducing mechanism system such as a servo, and a reproduction signal processing system such as a digital signal decoding operation and an error correcting process. When an electronic watermark detecting circuit is built in an MPEG signal recording device or an interface device, the pre-stage portion is for example an MPEG signal reproducing device or a video server connected through a network.
The input interface
901
inputs an eight-bit wide transport stream or eight-bit wide program stream that synchronizes with the external interface clock of the pre-stage portion (hereinafter, both the streams are generally referred to as “stream”). The stream is output to the buffer
902
.
The buffer
902
has a clock changing function that causes a stream that synchronizes with an external interface clock to synchronize with an internal clock. In addition, the buffer
902
has a function for absorbing the discontinuity of a stream supplied to the barrel shifter
904
, the discontinuity taking place due to the fluctuation of the length of the code decoded by the variable length decoding device
905
. For example, the buffer
902
is composed of a FIFO (First-In First-Out). As a write clock for the FIFO memory, the external interface clock is used. As a read clock for the FIFO memory, the internal clock is used. Of course, the write clock of the FIFO memory may synchronize with the read clock thereof. However, generally, the write clock of the FIFO memory does not synchronize with the read clock thereof.
The video elementary stream extracting circuit
903
has a function for extracting a video elementary stream from the input stream. The video elementary stream extracting circuit
903
delays the input stream by the number of clock pulses required to detect the video elementary stream and outputs the resultant frame and a valid flag that represents that each byte of the output stream is contained in the video elementary stream. The video elementary stream extracting circuit
903
is disclosed in for example Japanese Patent Laid-Open Publication No. 2001-345769.
The video elementary stream is a stream placed in a payload of a video PES (Packetized Elementary Stream) (the payload is a remaining portion of a video PES after a PES header is removed therefrom). The video elementary stream is defined in ISO 13818-1.
The barrel shifter
904
is driven by the internal clock whose clock frequency is approximately twice as high as the external interface clock (hereinafter, the internal clock is referred to as two-multiple clock). The barrel shifter
904
continuously inputs an eight-bit wide stream and outputs a stream having a width of 1 to 32 effective bits. Next, the operation of the barrel shifter
904
will be described in detail. The barrel shifter
904
shifts out bits (or proximately decoded bits) designated by the controlling portion
906
from an output shift register of 32-bit width at each two-multiple clock pulse. An output of each register of the output shift register is also supplied to the variable length decoding device
905
. When those bits are shifted out, bits that reside in the output shift register are shifted to the beginning portion by bits that have been shifted out. Insufficient bits at the end portion of the output shift register are compensated with each bit of a bit group of the stream that is intermittently input in a unit of byte. After a variable length code is decoded, all bits of at most 32-bit variable length code are arranged in the output sh
McGinn & Gibb PLLC
NEC Corporation
Williams Howard L.
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