Method to reduce time to dynamic steady-state condition

Details Method to reduce time to dynamic steady-state condition Method to reduce time to dynamic steady-state condition

2002-08-20

2004-03-02

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Accelerating switching

C327S198000

Reexamination Certificate

active

06700430

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microprocessors, and more particularly to the powering of clock circuits in microprocessors.
BACKGROUND OF THE INVENTION
The user of partially depleted/silicon-on-insulator (PD/SOI) transistors is known in the industry. One use is in circuits of a microprocessor.
FIG. 1
illustrates a conventional microprocessor. The microprocessor
100
comprises a clock circuit
104
and a power supply and control
102
for the clock circuit
104
. The power supply
102
also powers other circuits on the microprocessor, such as low duty cycle circuits
106
. The power supply and control
102
can be off-chip as well.
FIG. 2
illustrates a conventional inverter circuit utilizing PD/SOI transistors. The inverter circuit
200
is a basic building block for higher-order circuits of the microprocessor
100
, including the clock circuit
104
and the low duty cycle circuits
106
. The inverter circuit
200
comprises a PD/SOI n-channel metal oxide semiconductor field effect transistor (MOSFET)
202
and a PD/SOI p-channel MOSFET
204
, coupled as shown. The inverter circuit
200
is powered with a voltage V
DD
.
FIG. 3
illustrates a cross-sectional view of a PD/SOI transistor. The transistor
300
comprises a substrate
314
. Formed in the substrate is a source
302
, a drain
304
, and a floating body region
310
between the source
302
and drain
304
. Above the source
302
, drain
304
, and body region
310
are a gate
306
and an insulator layer
308
. The insulator layer
308
can be oxide, nitride, a combination of oxide and nitride, or some other insulating material. Another insulator layer
312
resides between the floating body
310
and the rest of the substrate
314
, isolating the body
310
. When the transistor
300
is charged after being dormant for a significant amount of time, excess charge builds within the floating body
310
due to slow carrier recombination/generation processes. As the excess charge builds, the threshold voltage of the transistor
300
is lowered and varies over time.
In the context of the inverter circuit
200
, a normal operating voltage V
DD
is applied to the inverter circuit
200
. Excess charge builds up in the body
310
during this initial voltage application. The excess charge lowers and varies the threshold voltage of the inverter circuit's transistors
202
and
204
over time, which in turn causes the switching delay of the inverter circuit
200
to vary over time. This variation is known in the industry as the “hysteresis” effect. Eventually, the transistors
202
and
204
of the inverter circuit
200
stabilize to their dynamic steady state (DSS) conditions.
When the inverter circuit
200
is used for the clock circuit
104
, the hysteresis effect causes the timing of both the rise and fall of each clock cycle to vary. Thus, while the hysteresis effect persists, reliability of transmitted data could be compromised. Typically, data transmission is delayed until the transistors
202
and
204
of the invert circuit
200
reach their DSS condition, stabilizing the clock cycles. However, the time required for this could be lengthy, such as for several microseconds.
Accordingly, there exists a need for a method for reducing the time for a PD/SOI-based circuit to reach a dynamic steady state. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method for reducing the time for a partially depleted/silicon-on-insulator (PD/SOI) based circuit to reach a dynamic steady state pre-conditions the PD/SOI-based circuit by initially charging the circuit at a voltage greater than the normal operating voltage. The circuit is then charged at the normal operating voltage after a predetermined amount of time. By pre-conditioning the circuit in this manner, the amount of time required for the PD/SOI transistors of the circuit to reach their dynamic steady state (DSS) condition is shortened.


REFERENCES:
patent: 5514951 (1996-05-01), Halim et al.
patent: 6492848 (2002-12-01), Lee
Pelella, M.M. et al., Analysis and Contol of Hysteresis in PD/SOI CMOS, IEDM, Washington, D.C., Dec. 1999.

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