Surface shape recognition apparatus

Image analysis – Applications – Personnel identification

Reexamination Certificate

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Details

C382S115000, C345S174000, C340S005520, C340S005530, C713S186000

Reexamination Certificate

active

06714666

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a surface shape recognition apparatus and, more particularly, to a surface shape recognition apparatus for recognizing the small surface shape pattern of a human finger or animal nose.
In the social environment of today where the information-oriented society is developing, the security technology has taken a growing interest. For example, in the information-oriented society, a personal authentication technology for constructing an electronic money system is an important key. In fact, authentication technologies for implementing preventive measures against burglary and illicit use of cards are under active research and development (for example, Yoshimasa Shimizu, “A Study on the Structure of a Smart Card with the Function to Verify the Holder”, Technical Report of IEICE, OFS92—32, pp. 25-30, (1992)).
Such authentication techniques include various schemes using a fingerprint or voiceprint. Especially, many fingerprint authentication techniques have been developed. Fingerprint authentication schemes are roughly classified into optical read schemes and schemes of converting the three-dimensional pattern on the skin surface of a fingertip into an electrical signal using human electrical characteristics and outputting the electrical signal.
In an optical read scheme, a fingerprint is received as optical image data mainly using light reflection and a CCD images sensor and collated (Japanese Patent Laid-Open No. 61-221883).
Another scheme has also been developed, in which a piezoelectric thin film is used to read the pressure difference on a finger skin surface (Japanese Patent Laid-Open No. 5-61965). As a scheme of converting a change in electrical characteristics due to contact of skin into an electrical signal distribution to detect the shape of fingerprint, an authentication scheme of detecting a resistance or capacitance change amount using a pressure sensitive sheet has been proposed (Japanese Patent Laid-Open No. 7-168930).
However, of these techniques, the scheme using light is hard to achieve size reduction and versatility, and its application purpose is limited. The scheme of sensing the three-dimensional pattern at a fingertip can hardly be put into practical use and is poor in reliability because of special materials and difficulty in working.
A capacitive fingerprint sensor using an LSI manufacturing technology has also been proposed (Marco Tartagni and Roberto Guerrieri, A 390 dpi Live Fingerprint Imager Based on Feedback Capacitive Sensing Scheme, 1997 IEEE International Solid-State Circuits Conference, pp. 200-201 (1997)). In this method, small sensors two-dimensionally arrayed on an LSI chip detect the three-dimensional pattern of a skin using a feedback electrostatic capacitance scheme. For this capacitive sensor, a plate is formed on the uppermost layer of LSI interconnections, and a passivation film is formed thereon.
When a fingertip comes into contact with this sensor, the skin surface functions as a second plate which is spaced apart by an insulating layer formed by air. Sensing is done on the basis of the distance difference between the skin surface and the plate, thereby detecting the fingerprint. In this technique, a reference plate is arranged near the plate on the uppermost layer, and the difference from this reference plate is used for actual sensing. As characteristic features of this structure, no special interface is required, and the size can be reduced, unlike the conventional optical scheme.
In principle, the fingerprint sensor has a sensor electrode formed on a semiconductor substrate and a passivation film formed on the sensor electrode, in which the capacitance between the skin and the sensor is detected through the passivation film to detect a small three-dimensional structure.
The conventional capacitive fingerprint sensor will be briefly described with reference to the accompanying drawings. This capacitive sensor has a structure shown in FIG.
10
. An interconnection
403
is formed via a lower insulating film
402
on a semiconductor substrate
401
having LSIs formed thereon, and an interlevel insulator
404
is formed thereon.
Sensor electrodes
406
each having, e.g., a rectangular planar shape are formed on the interlevel insulator
404
. The sensor electrode
406
is connected to the interconnection
403
through a plug
405
in the through hole formed in the interlevel insulator
404
. A passivation film
407
is formed on the interlevel insulator
404
to cover the sensor electrodes
406
, thereby forming a sensor element. As shown in
FIG. 11
, a plurality of sensor elements are two-dimensionally arrayed while preventing the sensor electrodes
406
of adjacent sensor elements from coming into contact with each other.
The operation of the capacitive sensor will be described next. To detect a fingerprint, a finger whose fingerprint is to be detected comes into contact with the passivation film
407
first. As the finger comes into contact, the skin in contact with the passivation film
407
on the sensor electrode
406
functions as an electrode, so a capacitance is formed between the skin and the sensor electrode
406
. This capacitance is detected through the interconnection
403
. The fingerprint at the fingertip is formed by the three-dimensional pattern of the skin. Hence, when the fingertip is brought into contact with the passivation film
407
, the distance between the sensor electrode
406
and the skin serving as an electrode changes between the ridge portion and the valley portion of the skin surface. This difference in distance is detected as the difference in capacitance. Hence, the three-dimensional pattern on the skin surface can be obtained by detecting the distribution of capacitance that changes between the sensor electrodes. Thus, the small three-dimensional pattern on the skin can be sensed by this capacitive sensor.
Such a capacitive fingerprint sensor requires no special interface and enables size reduction, unlike the conventional optical sensor.
This capacitive sensor can be integrally mounted on an integrated circuit (LSI) chip which integrates the following sections. More specifically, the above-described capacitive sensor can be mounted on an integrated circuit chip which integrates a capacitance detection circuit for detecting the capacitance of the sensor electrode
406
, a processing circuit for receiving and processing the output from the capacitance detection circuit, a storage circuit storing fingerprint data for collation, and a comparison/collation circuit for comparing and collating the fingerprint data in the storage circuit with a fingerprint detected by the capacitance detection circuit and processed by the processing circuit. When these units are formed on one integrated circuit chip, information can hardly be altered in data transfer between the units, and security performance can be improved.
A capacitance detection sensor using such an LSI technology is described in, e.g., “ISSCC DIGEST OF TECHNICAL PAPERS” FEBRUARY 1998 pp. 284-285.
FIG. 12
shows a conventional capacitance detection circuit for detecting an electrostatic capacitance formed between finger skin and an electrode to detect the three-dimensional pattern on the skin surface. Referring to
FIG. 12
, a detection element
50
outputs, as a voltage signal, a value Cf of electrostatic capacitance formed between the sensor electrode
406
and a surface
400
of a finger in contact. A capacitance detection circuit
500
comprises a signal generation circuit
510
and output circuit
520
. The sensor electrode
406
of the detection element
50
is connected to the input side of a current source
511
of a current I through an NMOS transistor Q
2
. A node N
1
between the sensor electrode
406
and the transistor Q
2
is connected to the input side of the output circuit
520
. A power supply voltage VDD is applied to the node N
1
through a PMOS transistor Q
1
. The node N
1
has a parasitic capacitance Cp
0
. Signals {overscore (PRE)} and RE are supplied to the gate terminals o

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