Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-08-15
2004-05-25
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S531000
Reexamination Certificate
active
06740956
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to metal traces and, more particularly, to a metal trace with reduced RF impedance resulting from the skin effect.
2. Description of the Related Art
Metal traces are common integrated circuit elements that are used in a multi-level interconnect structure to connect together various elements of a circuit. In addition, a metal trace can be used to form an integrated circuit inductor by forming the trace to have a number of coils or loops. Inductors are common circuit elements in radio frequency (RF) applications, such as digital cellular telephones.
FIG. 1A
shows a plan view that illustrates a prior art integrated circuit inductor
100
.
FIG. 1B
shows a cross-sectional view taken along lines
1
B—
1
B of FIG.
1
A.
FIG. 1C
shows a cross-sectional view taken along lines
1
C—
1
C of FIG.
1
A.
FIG. 1D
shows a cross-sectional view taken along lines
1
D—
1
D of FIG.
1
A.
As shown in
FIGS. 1A-1D
, inductor
100
is formed on top of a four-metal layer interconnect structure that includes a fourth layer of insulation material I
4
, and a metal trace
110
that is formed on insulation layer I
4
from a fourth metal layer M
4
. In addition, the metal interconnect structure includes a fifth layer of insulation material I
5
that is formed on metal trace
110
, and a via
112
that is formed through insulation layer I
5
to make an electrical connection with metal trace
110
.
As further shown in
FIGS. 1A-1D
, inductor
100
includes a metal trace
114
that is formed on top of the fifth layer of insulation material I
5
from a fifth metal layer M
5
. Metal trace
114
, which has a width W and a depth D, has a first end
120
that is formed over via
112
to make an electrical connection with via
112
, and a second end
122
. Metal trace
114
, which makes one and a half loops in the same plane, is typically formed on top of the metal interconnect structure to avoid inducing currents in the substrate.
One important measure of a metal trace is the RF impedance of the trace, which affects the quality factor or Q of an inductor formed from the metal trace. High Q inductors are desirable in a number of RF circuits, such as resonant circuits. The Q of an inductor is a measure of the ratio of magnetic energy stored in the inductor versus the total energy fed into the inductor, and is given by equation (EQ.) 1 as:
Q=&ohgr;L/Z,
EQ. 1
where &ohgr; is related to the frequency f of the signal applied to the inductor (&ohgr;=2(pi)(f)), L represents the inductance of the inductor, and Z represents the RF impedance of the inductor. (Impedance is the vector sum of resistance and reactance, and introduces a phase shift.) Thus, as indicated by EQ. 1, the smaller the impedance, the higher the Q of the inductor.
One problem with metal traces is that when gigahertz-frequency signals are placed on the trace, the skin effect causes current to flow primarily at the surface. This effectively increases the RF impedance of the trace which, in turn, lowers the Q of an inductor formed from the trace.
One common approach to reducing the impedance of an integrated circuit inductor is to increase the size of the metal trace. However, in integrated circuit applications, there are practical limitations to the size of the metal trace. As a result, there is a need for a metal trace with reduced RF impedance which, in turn, allows a high Q integrated circuit inductor to be realized from the trace.
SUMMARY OF THE INVENTION
The present invention provides a metal trace that has reduced RF impedance at gigahertz frequencies. When the metal trace is formed to have a number of loops, the looping metal trace forms an integrated circuit inductor, while the reduced RF impedance increases the Q of the inductor.
A semiconductor structure in accordance with the present invention includes a layer of insulation material that is formed over a semiconductor substrate. In addition, the semiconductor structure includes a metal trace that is formed in the layer of insulation material. The metal trace has a base region and a plurality of spaced-apart fingers that extend away from the base region. The metal trace can be formed to have a number of loops, and the loops can be formed to lie substantially in the same plane.
The present invention also includes a method of forming a semiconductor structure that includes the steps of forming a layer of insulation material over a semiconductor substrate. The layer of insulation material has a first opening that defines a first side wall and an opposing second side wall.
The method also includes the steps of forming a first layer of conductive material on the layer of insulation material to fill up the first opening, and anisotropically etching the first layer of conductive material to form a first conductive spacer that adjoins the first side wall and the second side wall, and a second opening.
The method further includes the step of forming a first layer of isolation material on the layer of insulation material and the first conductive spacer to fill up the second opening. In addition, the method includes the step of forming a conductive region on the first conductive spacer and the first layer of isolation material. The conductive region makes an electrical connection with the first conductive spacer.
The method can also include the step of anisotropically etching the first layer of isolation material to form a first isolation spacer that adjoins the first conductive spacer, and a third opening. Further, the method can include the steps of forming a second layer of conductive material on the layer of insulation material to fill up the third opening, and anisotropically etching the second layer of conductive material to form a second conductive spacer that adjoins the first isolation spacer, and a fourth opening.
In addition, the method can include the step of forming a second layer of isolation material on the layer of insulation material and the first conductive spacer to fill up the fourth opening. The conductive region makes an electrical connection with the first and second conductive spacers.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 3573540 (1971-04-01), Osepchuk
patent: 4165558 (1979-08-01), Armitage, Jr. et al.
patent: 5434094 (1995-07-01), Kobiki et al.
patent: 5952704 (1999-09-01), Yu et al.
patent: 5998299 (1999-12-01), Krishnan
patent: 6191023 (2001-02-01), Chen
patent: 6326673 (2001-12-01), Liou
patent: 6444517 (2002-09-01), Hsu et al.
Drury Robert
Hopper Peter J.
Hwang Kyuwoon
Johnson Peter
Mian Michael
National Semiconductor Corporation
Nguyen Tuan H.
Pickering Mark C.
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