Method of forming first level of metallization in DRAM chips

Details Method of forming first level of metallization in DRAM chips Method of forming first level of metallization in DRAM chips

2000-05-18

2004-04-06

Goudreau, George (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S201000, C438S275000, C438S710000, C438S725000, C438S241000, C438S253000, C438S256000, C438S258000

Reexamination Certificate

active

06716764

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to a new method of forming contacts and metal lands at the first level (M
0
) of metallization to significantly improve device performance.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits and particularly in dynamic random access memory (DRAM) chips, the metal interconnect at the first level, referred to herein below as the M
0
level, is extensively used to address memory cells of the chip. In essence, it is used to make contacts with the diffusion regions (drain/source) of all the insulated gate field effect transistors (IGFETs) driven by the same bit line (BL) and to interconnect the gate conductors of all the IGFETs driven by a same word line (WL) to their respective driving IGFET at the chip periphery. Each bit line consists of a metal land which is formed at the M
0
photolithography level.
The essential steps of a conventional contact and metal land fabrication process will be briefly described by reference to FIG.
1
and
FIGS. 2A-2I
. After these steps been completed, the contacts and metal lands at the first level of metallization (M
0
interconnect level) and the bit lines of the DRAM chip are fabricated.
FIG. 1
schematically illustrates a state-of-the-art semiconductor structure
10
, which is a part of a wafer at the initial stage of the formation process. Structure
10
, is basically comprised of a silicon substrate
11
, with N+ and P+ diffusion regions
12
A, and
12
B, respectively (generically referenced to as region
12
) formed therein and a plurality of gate conductor stacks
13
, on a SiO
2
layer forming the gate dielectric of IGFETs as standard. A gate conductor (GC) stack consists of a composite doped polysilicon/tungsten silicide (WSi
x
)/Si
3
N
4
cap structure. As apparent in
FIG. 1
, the Si
3
N
4
cap is extended to cover the GC stack sidewall for passivation purposes, forming the so-called GC spacers. At the chip surface, two different zones are to be considered. First, the “array” wherein the memory cells are fabricated. Each elementary memory cell is comprised of an IGFET and its associated storage capacitor that is formed in a deep trench as standard. In the other zone referred to as the “support”, one can find addressing and driver circuits. Structure
10
, is coated with a boro-phospho-silicate-glass (BPSG) layer
14
, and an overlying tetra-ethyl-ortho-silicate (TEOS) oxide layer
15
. These layers are conformally deposited onto structure
10
, by LPCVD as standard. As apparent in
FIG. 1
, structure
10
, has a substantially planar surface.
Now, two types of contact holes are created depending upon their location at the structure
10
, surface. First, contact holes referred to as CB holes bearing numeral
16
, as clearly seen in
FIG. 2A
, are etched through layers
14
and
15
, in the “array” area.
Now referring to
FIG. 2B
, a doped polysilicon layer
17
, is conformally deposited onto the structure
10
, to completely overfill the contact hole
16
. Next, the doped polysilicon layer
17
, is dry etched in a plasma until the TEOS layer
15
, surface is reached. The etching is continued to produce a recess (CB recess) in the remaining polysilicon fill
17
, as shown in FIG.
2
C. CB recesses will be subsequently filled with metal to form lands that will be used as the bit lines of the memory cell. This over etching is determined by time and is very critical because of its sensitivity to the etch duration and thickness non-uniformities across the wafer. This over etching is carefully conducted in order not to expose the gate conductor stack
13
, sidewall. If CB recess is too deep, because CB recess etch chemistry has a poor selectivity between the Si
3
N
4
forming the GC spacer and the doped polysilicon of layer
17
, the GC spacer can be partially removed exposing the WSi
x
material. In this case, an electrical short between bit and word lines will appear at the end of the fabrication process. The purpose of these steps is thus to produce conductive studs
17
, that will subsequently allow an electrical contact between metal lands of the bit lines and N+ type diffusion regions
12
A (e.g. a drain region common to two adjacent IGFETs, as illustrated in
FIG. 2C
) in the substrate
11
.
Now, turning to
FIG. 2D
, structure
10
, is coated first with a 90 nm thick anti-reflective coating (ARC) layer
18
, which fills CB recess
16
, above polysilicon stud
17
, then with a 850 nm thick photo resist material
19
. These chemicals are supplied by SHIPLEY, Malborough, Mass, USA, under brand names AR3 and UV2HS, respectively. After deposition, the photo resist layer
19
, is baked, exposed and developed as standard to leave a patterned layer, that will be referred to herein below as the CS (Support Contact) mask. The purpose of this CS mask
19
, is to define the locations of the contacts to be opened between metal lands of the first level of metallization (M
0
) and the diffusion regions
12
B, at the surface of structure
10
, in the support area.
Using the CS mask
19
, contact holes are etched through layers
18
,
15
,
14
and the Si
3
N
4
cap of the GC stack
13
, in the support area at desired locations to expose the WSi
x
material of the GC stacks of IGFETs and the P+ diffusion regions
12
B, of the substrate
11
. These contact holes will be referred to herein below as the gate conductor contact (CG) and diffusion contact (CD) holes bearing numerals
20
and
21
, in
FIG. 2E
, respectively. The above CS etch process chemistry has a poor selectivity to silicon, so that an undesired significant overetch of the P+ diffusion region
12
B, (at the bottom of contact hole
21
) is produced as clearly apparent in
FIG. 2E
, reducing its active section. The amount of implanted dopants in this P+ diffusion region is significantly diminished during this overetch, depleting thereby the dopant concentration therein. These two drawbacks have a great impact on diffusion region
12
B, resistivity and thus on IGFET source/drain saturation current. A similar defect is also visible at the bottom of contact hole
20
, but is less critical as soon as WSi
x
material is not completely removed.
Now, turning to
FIG. 2F
, structure
10
, is coated again with a 90 nm thick anti-reflective coating (ARC) layer
22
, which fills contact holes
16
,
20
and
21
, and then with a 850 nm thick photo resist material
23
. Same chemicals and processes as in the previous CS mask photolithography step are used. After deposition, the photo resist layer
23
, is baked, exposed and developed as standard to leave a patterned layer, that will be referred to herein below as the M
0
mask
23
. The purpose of this M
0
mask
23
, is to define the locations of metal lands of the first level of metallization at the surface of structure
10
. As visible in
FIG. 2F
, because ARC material of layer
22
, is not a good planarization medium, certain contact holes
21
, will not be completely filled. Other contact holes
20
, may exhibit a large void which is not critical in the extent the top of the contact hole is closed as shown in FIG.
2
F.
After the M
0
mask
23
, has been defined, the process continues with the M
0
etch process to remove 270 nm of TEOS layer
15
, at locations not protected by said M
0
mask
23
, in two processing steps.
The first step so-called “ARC OPEN” etches the ARC layer
22
, down to the TEOS layer
15
, top surface. At this stage of the metal land formation process, the structure
10
, is shown in FIG.
2
G. As apparent in
FIG. 2G
, openings in M
0
mask
23
, have tapered sidewalls, reducing thereby the process window of the previous photolithography steps. In addition, ARC material of layer
22
, at bottom of contact holes
21
, is completely removed, exposing again the P+ diffusion region
12
B, to the next etch step.
The second step etches about 270 nm of the TEOS layer
15
, to produce the desired recesses wherein the M
0
metal

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