Expandable flash-memory mass-storage using shared buddy lines an

Details Expandable flash-memory mass-storage using shared buddy lines an Expandable flash-memory mass-storage using shared buddy lines an

1997-09-29

1998-10-13

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

36518901, 365218, G11C 1300

Patent

active

058222510

ABSTRACT:
A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to the flash buffer chips. Two flash-specific DMA controllers are provided, each with four DMA state machines for controlling the four banks of flash-memory chips attached to a flash buffer chip. This allows for four-way interleaving. Two flash buses connect the two DMA controllers to flash buffer chips. The flash bus has a narrow byte-wide interface to send command, address, and data bytes from the DMA controller to the flash buffer chips. These command, address, and data bytes are then passed through the flash buffer chip to the flash-memory chips. Two additional command signals on the flash bus are used to select and control the flash buffer chips. Busy signals from all flash-memory chips in a bank are connected together, and the four busy signals from the four banks are time-multiplexed to a single common busy line for the flash bus. The four DMA state machines each monitor one period of the busy line, allowing four flash operations to be monitored at a time, even though only one data transfer can occur across the flash bus.

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