Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device
Reexamination Certificate
2002-07-18
2004-05-04
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
C257S494000, C257S903000, C438S275000
Reexamination Certificate
active
06730947
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuit apparatuses that require higher integration and their manufacturing methods.
BACKGROUND TECHNOLOGY
As radiations enter a semiconductor substrate including a semiconductor integrated circuit, the entered radiation particles generate electron-positive hole pairs in the process of loosing their energy due to the interaction with the atoms of the semiconductor substrate. Signals caused by the generated electrons or positive holes become noises, and may cause erroneous functions in the semiconductor integrated circuit apparatus.
In particular, &agr;-rays cause to generate numerous electron-positive hole pairs (hereafter referred to as “carriers”) in the semiconductor substrate. For example, when an &agr;-ray enters silicon, its flying distance is about 25 &mgr;m, and 1.4×10
6
electron-positive hole pairs are generated along that trajectory. As the generated minority carriers flow in an integrated circuit element region, the potential on the impurity region of the integrated circuit element region changes, which then causes a soft error.
For example, where an N
+
diffusion layer is formed in a P-type substrate, minority carriers are trapped in the following manner. Minority carriers that are generated in a depletion layer (electrons in this case) flow into the integrated circuit element region by the electric filed applied to the depletion layer. Minority carriers that are generated in the substrate spread within the substrate by diffusion. Those of the minority carriers diffused that reach the depletion layer flow into the impurity region, and the others may recombine with positive holes within the semiconductor substrate or may flow into electrodes on the side of the semiconductor substrate.
In the case of semiconductor integrated circuit apparatuses, radioactive elements included in a trace amount in the semiconductor package material and metal of wirings may emit &agr; rays. When the &agr; rays enter a semiconductor integrated circuit apparatus, there are cases in which a large amount of electron-positive hole pairs is generated, and information stored in the semiconductor integrated circuit such as a semiconductor memory may be destroyed. In this case, the semiconductor integrated circuit apparatus may cause &agr; ray soft errors.
To cope with such &agr; ray soft errors, there is a known technology to provide an embedded impurity layer. More specifically, an embedded impurity layer is provided on the entire area below integrated circuit elements that compose a memory cell array, to prevent minority carriers that are generated upon the incidence of &agr; rays from entering into the integrated circuit element region.
Among semiconductor integrated circuits, higher integrations are being promoted even in SRAMs (Static Random Access Memories) that are difficult to achieve large scale integrations compared to DRAMs (Dynamic RAMs). SRAMs are advantageous in high-speed reading, and are suitable for cash memories for systems in which the number of parts is limited such as mobile type equipment, personal computers and work stations. Many SRAMs are equipped with an embedded impurity layer to cope with &agr; ray soft errors.
A unit circuit that stores 1-bit information (a memory cell) in an SRAM includes a flip-flop circuit as a basic structure, in which a COMS circuit is indispensable. A memory cells are formed from N-well regions and P-well regions in a semiconductor substrate.
FIGS.
4
(
a
) and (
b
) each show a SRAM memory cell region, wherein (a) is a plan view of wells, and (b) shows a cross-sectional view taken along a line
4
B—
4
B of (a). As indicated in FIG.
4
(
a
), N-well regions NWEL and P-well regions PWEL are alternately arranged. Sections with hatched lines are regions that are used for one memory cell, and at least each of the cells is insulated and isolated from others by an element isolation film (for example, by a trench isolation or the like). Memory cells, each being composed of the hatched regions as a unit region, are integrated in an array.
As indicated in FIG.
4
(
b
), an embedded impurity layer is provided below each of the wells NWEL and PWEL across adjacent ones of the well regions. In here, an N-type layer B-N is provided as an embedded impurity layer. The N-type layer B-N is provided by, for example, forming a deep well in a P-type substrate P-sub. The N-type layer B-N may be provided across, for example, one memory block in its entirety. By this, minority carriers that are generated upon the incidence of &agr;-rays are prevented from flowing into the integrated circuit element region.
FIG. 5
shows a circuit diagram of one example of an SRAM memory. Inputs and outputs of CMIS inverters, each of which is composed of a P-channel MIS transistor Qp
1
(Qp
2
) and an N-channel MIS transistor Qn
1
(Qn
2
) between the power supply and the ground, are mutually connected, to thereby form flip-flops FF
1
and FF
2
.
Selection transistors Qs contribute to transmission of signals respectively on bit lines BLL and BLR (data to be written or to be read out) by controlling the potential on a word line WL. The selection transistors Qs may be composed of P-channel MIS transistors, or N-channel MIS transistors.
With the structure described above, the SRAM cell continuously maintains stored information as long as a power supply voltage VDD is applied, and a refreshing operation is not required. By its CMOS circuit, its current consumption in the standby mode is extremely small, and a high-speed access time is achieved.
The P-channel MIS transistors Qp
1
and Qp
2
and the N-channel MIS transistors Qn
1
and Qn
2
are formed in any of the N-well regions NWEL and P-well regions NWEL shown in FIGS.
4
(
a
) and (
b
), respectively. Also, the selection transistors Qs are formed in either the N-well regions NWEL or P-well regions NWEL.
In the SRAM cell having the structure described above, the power supply voltage VDD is supplied to the N-well region NWEL and an impurity region that forms the source region of the P-channel MIS transistors Qp
1
and Qp
2
that are composed there above. The power supply voltage VDD is supplied through vias from power supply lines that are arranged at predetermined locations that connect to power supply pads (not shown in the drawings).
On the other hand, the ground potential VSS is connected to the P-well region PWEL and an impurity region that becomes a drain region of the N-channel MIS transistors Qn
1
and Qn
2
that are composed there above. Also, a P
+
tap of a high concentration P-type region is provided in the P-well region PWEL for each of the cells (or at intervals of a predetermined distance). The P+taps of the respective cells are electrically connected to wirings that are arranged at specified locations, and connected to ground pads (not shown in the drawings).
In the SRAM cell described above, an embedded impurity layer of a first conductive type is provided to cope with &agr;-ray soft errors. In this case, each of the first well regions that are impurity regions of the first conductive type is electrically connected to the embedded impurity layer. In this case, a potential can be supplied with one wiring to the embedded impurity layer and the plural first well regions. In contrast, for the second well regions that are impurity regions of the second conductive type, a high concentration impurity region of the second conductive type (hereinafter, this impurity region is called a tap region) is provided for the wiring and the wiring connection region in each of the second well regions. In other words, the wirings (and taps) are required to be disposed at intervals of specified distances. The provision of such wirings and taps is one of the causes to hinder the reduction of cell areas.
SUMMARY OF THE INVENTION
The present invention has been made in view of the circumstances described above, and its object is to provide a semiconductor device having SRAMs which are provided with an embedded impurity layer for copi
Harness & Dickey & Pierce P.L.C.
Lewis Monica
Seiko Epson Corporation
Zarabian Amir
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