Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-05-06
2004-09-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S210130
Reexamination Certificate
active
06791880
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory. Specifically, the present invention relates to a read circuit for a non-volatile memory device.
BACKGROUND ART
Many electronic devices, such as computers, personal digital assistants, cellular telephones, digital cameras and similar systems and devices include processors and memory. The memory is used to store computer programs to be executed by the device and/or data operated on by the processors to achieve the functionality of the device. Many devices and systems require that this information be retained in permanent storage non-volatile medium so that the data and computer programs is not lost when power is removed.
Flash memory is an example of a non-volatile memory device. Flash memory devices use a memory cell transistor that is similar to a metal-oxide semiconductor field effect transistor (MOSFET) with an additional floating gate structure disposed in the insulating layer between the control gate, and the source and drain. The channel between the source and drain is separated from the floating gate by a thin dielectric layer.
Programming of a memory cell is done by applying the appropriate potentials to the control gate, source, and drain so that electrons are transferred to the floating gate through the thin dielectric layer. The addition of electrons to the floating gate increases the threshold voltage for the transistor above the value for an uncharged floating gate. A read operation is performed by biasing the source and drain while applying a read voltage that is above the threshold voltage (V
1
) for an unprogrammed cell and below the threshold voltage for a programmed cell. An unprogrammed cell will conduct current at the applied read voltage, and thus represents a logical “1”, whereas a programmed cell will not conduct, and represents a logical “0.” The erasure of a memory cell is carried out by applying potentials to the control gate, source, and drain so that electrons are removed from the floating gate, thus lowering the threshold voltage.
Conventional flash memory devices utilize transistors that store a single bit per transistor and have a floating gate that is a conductor, such as polysilicon. Multi-bit memory cells have been developed that allow for storing more than one bit per transistor. These transistors may use a single floating gate with multiple programming levels, a split floating gate to provide more than one charge storage site, or a dielectric layer (in place of a floating gate) in which charge may be locally stored in multiple sites.
An example of a dielectric layer used for charge storage is a composite ONO layer (silicon nitride sandwiched between two layers of silicon dioxide). This layer may be used in a dual-bit memory cell that can store two bits per cell; however, the aging and cycling characteristics of the ONO layer are different from the conventional polysilicon floating gate.
When used for charge storage in a memory cell, an ONO layer may develop an increase in charge loss with cycling, giving rise to difference I-V characteristics at the end of life as compared to the I-V characteristics at the beginning of life for the device. In order to accommodate the changing I-V characteristics in the read operation, a dynamic reference array is used in place of a static reference. A dynamic reference array includes a set of memory cells that are programmed and erased along with the core memory cells of a flash memory device. Thus, the aging associated with the ONO layer essentially becomes a common mode error that can be canceled out by being introduced at both inputs of the comparator used in the read operation.
Although the error produced by aging of memory cells using an ONO layer can be dealt with by using a dynamically programmed reference array, there is still a problem with respect to the overall change in current loads in the read circuit. Although the difference error may be eliminated, the overall change in current levels is still a concern with respect to the operation of the read circuit. Since aging typically produces an increase in the cell drain-source current (I
ds
) at a given gate voltage (V
g
), the read circuit will generally have to deal with overall higher currents towards the end of life (EOL) as compared to the beginning of life (BOL), and thus there is uncertainty whether the read circuit will continue to perform properly with age.
DISCLOSURE OF THE INVENTION
A flash memory read circuit having adjustable current sources to provide end of life simulation is disclosed. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with tile reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
In an embodiment of the present invention, a non-volatile memory cell is coupled to a sense amplifier by a first cascode circuit that performs a current to voltage conversion to provide a voltage signal to one input of the sense amplifier. An adjustable current source is connected in parallel with the memory cell so that the total current input to the first cascode circuit may be adjusted. A reference current source is coupled to a second input of the sense amplifier by a second cascode circuit. The reference current source also has an adjustable current source connected in parallel, so that the total current input into the second cascode circuit may be adjusted.
In an embodiment of the present invention, a non-volatile memory cell is coupled to a sense amplifier by a first cascade circuit that performs a current to voltage conversion to provide a voltage signal to one input of the sense amplifier. An adjustable current source is connected in parallel with the memory cell so that the total current input to the first cascode circuit may be adjusted. A reference current source is coupled to a second input of the sense amplifier by a second cascode circuit. The reference current source comprises at least two reference memory cells. The reference memory cells may or may not be dynamically programmed. Each of the reference memory cells has an adjustable current source connected in parallel, so that the total current input into the second cascode circuit may be adjusted.
REFERENCES:
patent: 2002/0145910 (2002-10-01), Kern et al.
Chen Pau-Ling
Hamilton Darlene
Hsia Edward
Kurihara Kazuhiro
Le Binh Quang
FASL LLC
Hoang Huan
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