Piercer combined prober for CU interconnect water-level...

Details Piercer combined prober for CU interconnect water-level... Piercer combined prober for CU interconnect water-level...

2002-01-11

2004-04-27

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S761010

Reexamination Certificate

active

06727719

ABSTRACT:

TECHNICAL FIELD
The present invention relates to methods and apparatus for the testing of semiconductor devices. Specifically, the present invention relates to apparatus and methods thereof, which facilitate the creation of a temporary electrical connection with semiconductor devices for the purpose of testing the functionality of the semiconductor devices. The present invention also relates to electrical prober devices and methods thereof.
BACKGROUND OF THE INVENTION
Usually in the field of manufacture of semiconductor devices, such as integrated circuits (ICs), and during one of the final stages of the manufacture, the electrical characteristics of semiconductor devices, called IC chips, formed on a silicon wafer or the like are examined. Such examination is normally effected prior to cutting the wafer to divide the same into respective IC chips. For the sake of such examination, an integrated-circuit tester, called an IC tester, and a probing apparatus, called a wafer prober, are used. The examination itself of the electrical characteristics of each of the IC chips is carried out actually by the IC tester, and the wafer prober is used in order to establish an electrical connection between the IC tester and each of the IC chips on the wafer.
Manufacturers of semiconductor products thus commonly test their products prior to shipping them to their customers. These tests are usually performed both at the wafer level (“wafer sort”), where the semiconductors are remain in the form in which they were manufactured, and at the package level (“package sort”), after the wafer has been sawn up and the individual chips have been mounted into their protective carriers. To perform these tests, a temporary, non-destructive electrical connection must be formed between the semiconductor device and the testing apparatus. The device used to perform this function at the wafer sort stage is generically known as a “wafer probe card”. Thus generally, when the electrical characteristics of a wafer chip are tested, respective probes contact a plurality of microscopic electrode pads on a chip and the electrical test is performed through these probes.
Individuals with ordinary skill in the art will be familiar with various types of wafer probe cards and associated probers. Those skilled in the art are also familiar with the conventional assemblies utilized to interface, both mechanically and electrically, the semiconductor test computer's “test head” with an automated wafer prober in which a wafer probe card is positioned. The purpose of a test head is generally to place the high speed “test electronics” needed to test certain types of electronic devices as close as possible to the device-under-test (DUT). This shorter path greatly facilitates the passing of signals between the test electronics and the DUT. Wafer probers may be implemented as automated or manually controlled devices. A wafer prober may be configured as a conductive metal prober.
The physical relationship between the test head and the wafer prober has, historically, been problematic. The electrical connection between the test head and the wafer prober is generally a rigid member and a number of inventions have been created with the goal of forcing the test head and prober into an idealized physical relationship. Unfortunately, these rigid systems are generally either unwieldy or unsuccessful in their goal of forcing the test head and the prober into alignment. The result of this is a lack of reliable electrical contact between the test head and the probe card. Another undesirable result of this technique is warping of probe cards due to the forces induced on them either directly by the test head or by the Prober-Tester Interface (PTI).
Copper deposition manufacturing processes are gradually being adopted for deep sub-micron semiconductor manufacturing due its associated low resistance. A thin protecting silicon dioxide dielectric film is usually capped on intermetal wafers to prevent copper degradation before electrical measurement. It is generally difficult for a conductive metal prober to pierce through the hard dielectric film of a semiconductor wafer requiring testing. Moreover, state-of-the-art prober tips are designed as round-shaped tips, resulting frequently in worn-out probers. Most importantly, a significant noise due to poor prober-to-bond-pad contact can cause inaccurate measurement results, even though metal probers successfully pierce through the protecting dielectric film.
Based on the foregoing, the present inventors have concluded that a need exists for an improved semiconductor wafer prober, which can overcome the aforementioned problems associated with prior art probers. The present inventors further realize that a need exists for a prober, which provides accurate and increasingly reliable electrical measurement data and a reduction in metal prober consumption.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an apparatus and method for testing the electrical characteristics of a semiconductor integrated circuit.
It another aspect of the present invention to provide an apparatus and method for piercing through a semiconductor layer to test electrical components configured below the semiconductor layer.
It is still another aspect of the present invention to provide a piercer, which is configured from a hard material, such as, for example, diamond or carborundum.
It is yet another aspect of the present invention to provide an apparatus and method for testing semiconductor wafers and integrated electrical components thereof based on a piercer combined with a prober.
It is still another aspect of the present invention to provide a cocentric double layer structure prober.
It is another aspect of the present invention to provide a piercer mounted as an outer layer surrounding an inner layer which functions as conductive metal prober.
It is also an aspect of the present invention to provide a dummy probe card, which can be installed with piercers made from a hard material such as, for example, diamond or carborundum.
It is yet an additional aspect of the present invention to provide a round tip metal probe, which can be utilized to measure electrical characteristics of a semiconductor wafer, including integrated circuit components thereof.
The above and other aspects of the present invention can thus be achieved as is now described. An apparatus and method for testing the electrical characteristics of a semiconductor integrated circuit are disclosed herein. In a first embodiment of the present invention, an outer layer surrounds an inside needle, such that the outer layer comprises a hard material, which can penetrate through a semiconductor layer to permit subsequent testing of at least one semiconductor integrated circuit component located below the semiconductor layer. The inside needle may be adapted to electrically contact one or more electrical semiconductor circuit components located below the semiconductor layer. The inside needle generally comprises a prober, while the outer layer generally comprises a piercer. The outer layer may be configured from a hard material, such as diamond or carborundum. The inside needle and the outer layer together form a concentric double layer structure prober. The outer layer generally comprises a sheath formed from a hard dielectric material, such that the sheath comprises a piercer.
In a second or alternative embodiment of the present invention, an apparatus for testing the electrical characteristics of a semiconductor integrated circuit can include a piercer comprising a hard material, wherein the piercer permits enhanced piercing of at least one semiconductor layer to thereby test at lea

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