ESD protection circuit for low amplitude signals

Details ESD protection circuit for low amplitude signals ESD protection circuit for low amplitude signals

2002-10-28

2004-05-18

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S090000, C361S119000

Reexamination Certificate

active

06738248

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to an ESD/over-voltage protection circuit for low amplitude signals.
Electrostatic discharge (ESD) is an event that can occur during the handling or processing of semiconductor devices. During a typical ESD event, a large amount of charge is deposited on a pad of an integrated circuit. If the charge is sufficient to increase the voltage level on the pad above the voltage level at which the circuit is intended to operate, the semiconductor devices connected to that pad can become damaged.
Complementary metal-oxide semiconductor (CMOS) devices are particularly susceptible to damage from ESD events because CMOS devices have a thin gate oxide layer. In addition, advancements in fabrication technology have enabled the geometries of semiconductor devices to be reduced progressively so that more devices can fit on a single integrated circuit. This has resulted in further reductions in the thickness of the gate oxide layers, making CMOS devices even more susceptible to damage by ESD events. Future thin oxide devices can also be damaged by repetitive exposure to voltages only slightly larger than a supply voltage.
Typical CMOS devices have therefore been protected by various types and combinations of resistors, punch-through devices, diodes, parasitic bipolar transistors, and silicon-controlled rectifiers (SCRs). For example, a typical ESD protection circuit includes a reverse-biased diode coupled between the signal trace and the relatively positive voltage supply rail, VDD and another reverse-biased diode coupled between the signal trace and the relatively negative voltage supply rail, VSS. However this ESD protection method is expected to be inadequate as the supply voltages and device sizes within integrated circuits continue to reduce.
A reverse-biased diode coupled between the signal trace and VDD does not begin to conduct current until the voltage on the signal trace rises above the voltage on VDD by 0.7 volts. If the integrated circuit has a nominal supply voltage of 1.0 volts, the resulting ESD diode turn-on voltage is about 1.7 volts. With the very thin gate oxide layers in technologies having such a low supply voltage, a voltage of 1.7 volts can damage the semiconductor devices that are coupled to the signal trace. Thus, this method ESD protection may not be sufficient for some current and future semiconductor technologies.
Improved protection circuits are therefore desired, which are capable of protecting against ESD events and repetitive exposure to voltages only slightly larger than a supply voltage.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to an over-voltage protected integrated circuit, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.
Another embodiment of the present invention is directed to an integrated circuit, which includes a discharge node, first and second input-output pads, and first and second differential signal traces, which are coupled to the first and second input-output pads, respectively. A first voltage protection circuit is coupled between the first signal trace and the discharge node and conducts current if a voltage on the first signal trace is at least a threshold voltage greater than or less than a voltage on the discharge node. A second voltage protection circuit is coupled between the second signal trace and the discharge node and conducts current if a voltage on the second signal trace is at least the threshold voltage greater than or less than the voltage on the discharge node.
Yet another embodiment of the present invention is directed to a method of protecting semiconductor devices that are coupled to an input-output signal trace from over-voltages on the signal trace. The method includes: (a) biasing the semiconductor devices between first and second voltage supply terminals; and (b) conducting current between the first signal trace and a discharge node when a voltage on the first signal trace is greater than or less than a voltage on the discharge node by at least a threshold voltage.


REFERENCES:
patent: 6400541 (2002-06-01), Brett

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