Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-07-07
2004-04-06
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S760000, C438S926000
Reexamination Certificate
active
06717267
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a multi-layered interconnection structure in which interconnections are formed in a plurality of layers over the main surface of a semiconductor substrate, and particularly to an improvement for reducing the noise superimposed on the signals transmitted through the interconnections or cross-talk.
2. Description of the Background Art
Semiconductor integrated circuits represented by the LSIs (Large Scale Integrated circuits) have a large number of semiconductor elements formed in active regions in the main surface of semiconductor substrates. These semiconductor devices are electrically isolated from each other by element isolation structure such as STI (Shallow Trench Isolation). The semiconductor elements are selectively connected through electric conductors (interconnections) to realize the function of an integrated circuit.
Usually, polysilicon which contains a dopant at a high concentration or metal is used as the material of the electric conductor. Used as the metal interconnections are aluminum, copper, tungsten, molybdenum, etc. The gate structure, which is an interconnection formed in close proximity to the main surface of the semiconductor substrate, is formed by using aluminum, polysilicon, polysilicon/metal silicide double-layer structure, tungsten, molybdenum, etc. Metals such as tungsten, cobalt, nickel, titanium, zirconium, platinum, etc. are used for the metal silicide.
Two methods have conventionally been suggested as methods for forming the interconnections. In a first method, an interconnection material is deposited over the entire main surface of a semiconductor substrate by CVD (Chemical Vapor Deposition), sputtering, etc. and then a resist is applied. Then it is patterned through a transfer process to form a resist mask. The interconnection material is then anisotropically etched by using the resist mask to form an interconnection pattern. This first method is referred to as “etching method” in this specification.
In a second method, a resist is applied on an insulating film formed on the main surface of a semiconductor substrate and the resist is patterned through a transfer process to form a resist mask. Then an anisotropic etching is performed by using this resist mask to selectively form trenches in the insulating film. Next the trenches are filled with an interconnection material by using CVD or deposition. Subsequently, the surface is smoothed out by CMP (Chemical Mechanical Polishing) so that the surface of the insulating film and the surface of the interconnection material approximately coincide with each other. This second method is referred to as damascene method.
First, an interconnection formation process by the etching method will be described.
FIGS. 27
to
29
are manufacture process diagrams showing a conventional interconnection formation process by the etching method.
The process shown in
FIG. 27
is performed first. In the process of
FIG. 27
, first, STIs
102
as the element isolation structure and MOSFETs as semiconductor elements are formed on the main surface of the semiconductor substrate
101
which is a silicon substrate. Each MOSFET has a pair of N
+
source/drain regions (a set of a source region and a drain region is referred to as “source/drain regions” together)
106
, a pair of N
−
source/drain regions
105
and a channel region
104
, which are regions selectively formed in the main surface of the semiconductor substrate
101
. A gate electrode having a double-layer structure of a doped polysilicon layer
108
and a tungsten silicide layer
109
is selectively formed on the main surface, which faces to the channel region
104
through a gate insulating film
107
. Further, the gate electrode is covered by sidewalls
111
with a silicon oxynitride film
110
interposed therebetween.
The STIs
102
are selectively formed in the main surface of the semiconductor substrate
101
to electrically separate adjacent MOSFETs. A channel stopper layer
103
is formed in the semiconductor substrate
101
prior to the formation of the MOSFETs.
After the formation of the MOSFETs and STIs
102
, an interlayer insulating film
112
is deposited over the main surface of the semiconductor substrate
101
so thick as to cover the sidewalls
111
. Next, through holes
113
are selectively formed in the interlayer insulating film
112
right above the N
+
source/drain regions
106
, and aluminum
114
is deposited to fill the through holes
113
and to cover the interlayer insulating film
112
. The aluminum plugs buried in the through holes
113
function as the source/drain electrodes of the MOSFETs.
The aluminum
114
may precipitate on the semiconductor substrate
101
to cause leakage, since the semiconductor substrate
101
is exposed in the bottoms of the through holes
113
. To prevent this, a barrier metal layer (not shown) is deposited on the bottoms and sides of the through holes
113
. TiN (titanium nitride) is used as the material of the barrier metal layer, for example.
Next, an ARC film (Anti Reflection Coating)
115
is deposited on the aluminum
114
. The ARC film
115
is deposited to prevent so-called halation in which exposure light used in a transfer process is reflected at the surface of the aluminum
114
to cause the resist pattern to be formed thinner than the designed form. Subsequently, a resist is applied on the ARC film
115
and a resist mask
116
is formed through a transfer process.
Next, the process shown in
FIG. 28
is performed. In the process of
FIG. 28
, first, an anisotropic etching is applied to the aluminum
114
by using the resist mask
116
to form aluminum interconnections
150
. An interlayer insulating film
117
is then deposited. At this time, along the main surface of the semiconductor substrate
101
, while a small step height
120
appears on the surface of the interlayer insulating film
117
in the area
118
where the density of the aluminum interconnections
150
, or the interconnection density, is high, a large step height
121
appears in the area
119
where the interconnection density is low. Such a large difference in level like the step height
121
causes problems in the later processes; this degrades the accuracy of patterning by transfer in the process of depositing aluminum on the interlayer insulating film
117
and forming a second aluminum interconnection through a transfer process, for example.
In order to avoid this problem, the interlayer insulating film
117
may be smoothed by CMP prior to the deposition of aluminum on the interlayer insulating film
117
. However, due to the uneven interconnection density, the CMP process cannot sufficiently smooth the nonuniform topography on the surface of the interlayer insulating film
117
.
A method for avoiding this problem is known, where, as shown in
FIG. 29
, dummy aluminum interconnections
122
which do not contribute to the operation of the MOSFETs are formed to fill the intervals between the less densely arranged aluminum interconnections
150
so as to compensate for the unevenness of the interconnection density. This method avoids the formation of areas with less densely arranged interconnections and reduces the step height
123
appearing on the surface of the interlayer insulating film
117
, thus enhancing the flatness of the surface of the interlayer insulating film
117
after CMP. In this way, the formation of the dummy interconnection pattern is considered to be essential to obtain improved flatness on the surface of the structure formed after CMP above the semiconductor substrate
101
.
Next, an interconnection formation process by the damascene method will be described. A technique for enhancing the operating speed of LSIs is known, where copper (Cu), which has lower interconnection resistance than aluminum (Al), is used as the interconnection material in the LSIs. For example, at 20° C., Cu has a resistivity of as low as 1.70 &mgr;&OHgr;.cm while that of Al is 2.74 &mgr;&OHg
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